[llvm] [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (PR #112250)

[Craig Topper via llvm-commits]

topperc wrote:

> I was recently looking at how the backend chooses to do an RVC encoding vs a regular encoding, and was fairly surprised that it's effectively implicitly done from the tablegen insts - rather than us having a separate table. I'm not sure how we would do a separate table (as it's not a HwMode thing, it's a per-instruction thing), but this is the kind of thing I think that cannot be caught with the implicit approach (even though there's no actual bug here).

I'm not sure I follow. The compression is done via the CompressPat class in Tablegen which links the compressed and uncompressed instruction names. That generates a MachineInstr compressor for size estimation, and a MCInst compressor for RISCVAsmPrinter and the assembler. Then one decompressor for the disassembler.

https://github.com/llvm/llvm-project/pull/112250