[llvm] AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (PR #112353)

[Petar Avramovic via llvm-commits]

================
@@ -178,7 +178,7 @@ void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
   if (MRI.constrainRegAttrs(ToReg, FromReg))
     MRI.replaceRegWith(FromReg, ToReg);
   else
-    Builder.buildCopy(ToReg, FromReg);
+    Builder.buildCopy(FromReg, ToReg);
----------------
petar-avramovic wrote:


```
bb.0:
  liveins: $sgpr0, $vgpr0_vgpr1
  %0:sgpr(p1) = COPY $vgpr0_vgpr1
  %1:sgpr(s32) = COPY $sgpr0
  %2:sgpr(s32) = G_CONSTANT i32 1
  %3:sreg_32(s32) = G_ICMP intpred(ne), %1:sgpr(s32), %2:sgpr
  %4:sgpr(s32) = G_AND %3:sreg_32, %2:sgpr
  G_STORE %4:sgpr(s32), %0:sgpr(p1) :: (store (s32), addrspace 1)
  S_ENDPGM 0
```

```
bb.0:
  liveins: $sgpr0, $vgpr0_vgpr1
  %0:sgpr(p1) = COPY $vgpr0_vgpr1
  %1:sgpr(s32) = COPY $sgpr0
  %2:sgpr(s32) = G_CONSTANT i32 1
  %3:sreg_32(s32) = G_ICMP intpred(ne), %1:sgpr(s32), %2:sgpr
  %3:sreg_32(s32) = COPY %4:sgpr(s32)
  %4:sgpr(s32) = G_AND %3:sreg_32, %2:sgpr
  G_STORE %4:sgpr(s32), %0:sgpr(p1) :: (store (s32), addrspace 1)
  S_ENDPGM 0
```

```
# After AMDGPURegBankCombiner
# Machine code for function replaceRegWith_requires_copy: IsSSA, NoPHIs, TracksLiveness

bb.0:
  liveins: $sgpr0, $vgpr0_vgpr1
  %0:sgpr(p1) = COPY $vgpr0_vgpr1
  G_STORE %4:sgpr(s32), %0:sgpr(p1) :: (store (s32), addrspace 1)
  S_ENDPGM 0

# End machine code for function replaceRegWith_requires_copy.
```


https://github.com/llvm/llvm-project/pull/112353