[llvm] [AMDGPU] Disable i16 -> i32 promotion in CGP for DAGISel (PR #112334)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff b3a8400afa460a8372016e1abe5729cd4949b7d2 d05a3222b5637cb3a8cec49acf882b6b7fdd76a4 --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h
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<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index c7bae4dd05..a5285da59d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6822,19 +6822,20 @@ static unsigned getExtOpcodeForPromotedOp(SDValue Op) {
   }
 }
 
-bool SITargetLowering::shouldPromoteUniformOpToI32(SDValue Op, EVT ExtTy, EVT OpTy) const {
-  switch(Op.getOpcode()) {
-    case ISD::SMIN:
-    case ISD::SMAX:
-    case ISD::UMIN:
-    case ISD::UMAX: {
-      if (!Subtarget->has16BitInsts() || OpTy.isVector())
-        return false;
-      unsigned Size = OpTy.getSizeInBits();
-      return !Op->isDivergent() && Size >= 2 && Size <= 16;
-    }
-    default:
-      return !isNarrowingProfitable(Op.getNode(), ExtTy, OpTy);
+bool SITargetLowering::shouldPromoteUniformOpToI32(SDValue Op, EVT ExtTy,
+                                                   EVT OpTy) const {
+  switch (Op.getOpcode()) {
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX: {
+    if (!Subtarget->has16BitInsts() || OpTy.isVector())
+      return false;
+    unsigned Size = OpTy.getSizeInBits();
+    return !Op->isDivergent() && Size >= 2 && Size <= 16;
+  }
+  default:
+    return !isNarrowingProfitable(Op.getNode(), ExtTy, OpTy);
   }
 }
 
@@ -6868,13 +6869,16 @@ SDValue SITargetLowering::promoteUniformOpToI32(SDValue Op,
     RHS = Op->getOperand(1);
   }
 
-  // For SIGN_EXTEND, check for an existing SIGN_EXTEND_INREG and reproduce that instead.
-  // It leads to better code generation.
-  // TODO: DAGCombiner should take care of that but the combine doesn't apply all the time.
-  const auto ExtendOp = [&, ExtOp = getExtOpcodeForPromotedOp(Op)](SDValue Op){
+  // For SIGN_EXTEND, check for an existing SIGN_EXTEND_INREG and reproduce that
+  // instead. It leads to better code generation.
+  // TODO: DAGCombiner should take care of that but the combine doesn't apply
+  // all the time.
+  const auto ExtendOp = [&, ExtOp = getExtOpcodeForPromotedOp(Op)](SDValue Op) {
     if (ExtOp == ISD::SIGN_EXTEND && Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
-      SDValue InRegSrc = DAG.getNode(ISD::ANY_EXTEND, DL, ExtTy, Op.getOperand(0));
-      return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtTy, {InRegSrc, Op->getOperand(1)});
+      SDValue InRegSrc =
+          DAG.getNode(ISD::ANY_EXTEND, DL, ExtTy, Op.getOperand(0));
+      return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtTy,
+                         {InRegSrc, Op->getOperand(1)});
     }
 
     return DAG.getNode(ExtOp, DL, ExtTy, {Op});

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https://github.com/llvm/llvm-project/pull/112334