[llvm] [LLVM][AArch64] Add register classes for Armv9.6 assembly (PR #111717)

[via llvm-commits]

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@@ -561,15 +564,31 @@ AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
   return MO.getImm() - 8;
 }
 
-template <unsigned Multiple>
+template <unsigned Multiple, unsigned Min, unsigned Max>
 uint32_t
-AArch64MCCodeEmitter::EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
-                                            SmallVectorImpl<MCFixup> &Fixups,
-                                            const MCSubtargetInfo &STI) const {
+AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
   assert(llvm::isPowerOf2_32(Multiple) && "Multiple is not a power of 2");
   auto RegOpnd = MI.getOperand(OpIdx).getReg();
   unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
-  return RegVal / Multiple;
+  assert(RegVal >= Min && RegVal <= Max && (RegVal & Multiple - 1) == 0);
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Lukacma wrote:

Could `Multiple - 1` be bracketed here to make it clear subtraction happens first. To me at least it wasn't obvious and got me confused for a while. 

https://github.com/llvm/llvm-project/pull/111717