[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

[Alex Bradbury via llvm-commits]

https://github.com/asb approved this pull request.

LGTM! Sorry for missing your request to re-review. I'm still missing the setup I had with Phabricator Herald :( But I'll try to improve my workflow.

https://github.com/llvm/llvm-project/pull/107446