[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

[Alex Bradbury via llvm-commits]

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@@ -1505,6 +1520,9 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   }
 
   switch (Opcode) {
+  case RISCV::PseudoMV_FPR16INX:
+    // MV is always compressible.
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asb wrote:

This comment made me double check, so sharing that process: Although we'd expect `c.li` to be used instead, `c.mv` can't handle an X0 operand. But from what I can see, we expand to ADDI and we have the obvious CompressPat from ADDI with X0 operand to c.li.

Perhaps expand the comment to "MV is always compressible (to either c.mv or c.li rd, 0)."

https://github.com/llvm/llvm-project/pull/107446