[llvm] [RISCV][MC] Support Assembling 48- and 64-bit Instructions (PR #110022)

[Jessica Clarke via llvm-commits]

jrtc27 wrote:

That addition came out of a bunch of discussion in https://github.com/riscv/riscv-isa-manual/issues/280 and resulted in https://github.com/riscv/riscv-isa-manual/commit/1d8fbc86a56d9b200bdc6fa5d20afa2aa0d3af8d, which post-dates 2.0, the description of which is where the quote you took comes from. "Table 70. RISC-V base opcode map, inst[1:0]=11" would benefit from clarifying that the encodings are reserved but not ratified for that specific use.

https://github.com/llvm/llvm-project/pull/110022