[llvm] [RISCV][MC] Support Assembling 48- and 64-bit Instructions (PR #110022)

[Sam Elliott via llvm-commits]

lenary wrote:

Is that the only documentation for the fact they're not ratified? Note the preface says "Standard instruction-length encodings have been defined for 48-bit, 64-bit, and 64-bit
instructions.", and Table 70 (which may be deemed not to be the canonical encoding information) also lacks that note.

This patch follows Table 70, and kicks the can down the road for much longer instructions, but maybe that still means there's no path to landing this and supporting hand-assembling wider instructions so they can be evaluated?

Alternatively, is it maybe worth adding a feature that we can put behind `-menable-experimental-extensions` so LLVM can support this without the wider encodings needing to be ratified?

https://github.com/llvm/llvm-project/pull/110022