[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)

[Matt Arsenault via llvm-commits]

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@@ -414,23 +418,25 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %
 }
 
 define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) {
-; GCN-LABEL: s_orn2_i16_multi_foldable_use:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_orn2_b32 s0, s2, s4
-; GCN-NEXT:    s_orn2_b32 s1, s3, s4
-; GCN-NEXT:    ; return to shader part epilog
+; GFX6-LABEL: s_orn2_i16_multi_foldable_use:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_orn2_b32 s0, s2, s4
+; GFX6-NEXT:    s_orn2_b32 s1, s3, s4
+; GFX6-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_orn2_i16_multi_foldable_use:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_orn2_b32 s0, s2, s4
-; GFX10-NEXT:    s_orn2_b32 s1, s3, s4
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX9-LABEL: s_orn2_i16_multi_foldable_use:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_xor_b32 s1, s4, -1
+; GFX9-NEXT:    s_or_b32 s0, s2, s1
+; GFX9-NEXT:    s_or_b32 s1, s3, s1
+; GFX9-NEXT:    ; return to shader part epilog
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arsenm wrote:

This is worse 

https://github.com/llvm/llvm-project/pull/106557