[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)

[Matt Arsenault via llvm-commits]

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@@ -348,6 +351,112 @@ bool AMDGPURegBankCombinerImpl::matchFPMed3ToClamp(MachineInstr &MI,
   return false;
 }
 
+bool AMDGPURegBankCombinerImpl::matchPromote16to32(MachineInstr &MI) const {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  const auto *RB = MRI.getRegBankOrNull(Dst);
+
+  // Only promote between 2 and 16 bits.
+  // For ICMP use the LHS of the comparison to get the type.
+  unsigned TyOpIdx = (MI.getOpcode() == AMDGPU::G_ICMP) ? 2 : 0;
+  LLT OpTy = MRI.getType(MI.getOperand(TyOpIdx).getReg());
+  if (OpTy.getScalarSizeInBits() < 2 || OpTy.getScalarSizeInBits() > 16)
+    return false;
+
+  // Only promote uniform instructions.
+  if (RB->getID() != AMDGPU::SGPRRegBankID)
+    return false;
+
+  // TODO: Support vectors. Vectors will create illegal ops, such as
+  // 2x32 exts, that we'd need to legalize.
+  // We could just scalarize all vectors but then we don't respect
+  // the legalizer's rules. Ideally we should be able to call
+  // the legalizer here, or this should move into the legalizer
+  // if it can tell between uniform and non-uniform values at
+  // some point.
+  if (DstTy.isVector())
+    return false;
+
+  // Promote only if:
+  //    - We have 16 bit insts (not true 16 bit insts).
+  //      - This is already checked by the predicate on the combine rule.
+  //    - We don't have packed instructions (for vector types only).
+  // TODO: For vector types, the set of packed operations is more limited, so
+  // may want to promote some anyway.
+  assert(STI.has16BitInsts());
+  return (DstTy.isVector() ? !STI.hasVOP3PInsts() : true);
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arsenm wrote:

This is an and and doesn't need parentheses. Shouldn't need the assert, it's implied by legality 

https://github.com/llvm/llvm-project/pull/106557