[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)

[Matt Arsenault via llvm-commits]

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@@ -348,6 +351,112 @@ bool AMDGPURegBankCombinerImpl::matchFPMed3ToClamp(MachineInstr &MI,
   return false;
 }
 
+bool AMDGPURegBankCombinerImpl::matchPromote16to32(MachineInstr &MI) const {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  const auto *RB = MRI.getRegBankOrNull(Dst);
+
+  // Only promote between 2 and 16 bits.
+  // For ICMP use the LHS of the comparison to get the type.
+  unsigned TyOpIdx = (MI.getOpcode() == AMDGPU::G_ICMP) ? 2 : 0;
+  LLT OpTy = MRI.getType(MI.getOperand(TyOpIdx).getReg());
+  if (OpTy.getScalarSizeInBits() < 2 || OpTy.getScalarSizeInBits() > 16)
+    return false;
+
+  // Only promote uniform instructions.
+  if (RB->getID() != AMDGPU::SGPRRegBankID)
+    return false;
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arsenm wrote:

Check this first, up when RB is assigned. Also this is a case where really what we care about is scalar, not uniformity 

https://github.com/llvm/llvm-project/pull/106557