[llvm] [RISCV][GISEL] Legalize G_INSERT and G_EXTRACT for scalable vectors (PR #108220)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 11 06:13:46 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Michael Maitland (michaelmaitland)
<details>
<summary>Changes</summary>
This PR legalizes G_INSERT and G_EXTRACT for scalable vectors. It is heavily based off the SelectionDAG code.
---
Patch is 47.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108220.diff
7 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (+5-3)
- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (+9-7)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+284)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrGISel.td (+76)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract.mir (+278)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert.mir (+278)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 925a1c7cf6aacc..96ca99a3871d8e 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -621,7 +621,8 @@ MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
#ifndef NDEBUG
assert(SrcTy.isValid() && "invalid operand type");
assert(DstTy.isValid() && "invalid operand type");
- assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
+ assert(TypeSize::isKnownLE(DstTy.getSizeInBits().getWithIncrement(Index),
+ SrcTy.getSizeInBits()) &&
"extracting off end of register");
#endif
@@ -797,8 +798,9 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
const SrcOp &Src,
const SrcOp &Op,
unsigned Index) {
- assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
- Res.getLLTTy(*getMRI()).getSizeInBits() &&
+ assert(TypeSize::isKnownLE(
+ Op.getLLTTy(*getMRI()).getSizeInBits().getWithIncrement(Index),
+ Res.getLLTTy(*getMRI()).getSizeInBits()) &&
"insertion past the end of a register");
if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 759201ed9dadc7..606929bb594e93 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1587,12 +1587,13 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
break;
}
- unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
- unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
+ TypeSize DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
+ TypeSize SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
if (SrcSize == DstSize)
report("extract source must be larger than result", MI);
- if (DstSize + OffsetOp.getImm() > SrcSize)
+ if (DstSize.getKnownMinValue() + OffsetOp.getImm() >
+ SrcSize.getKnownMinValue())
report("extract reads past end of register", MI);
break;
}
@@ -1609,13 +1610,14 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
break;
}
- unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
- unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
+ TypeSize DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
+ TypeSize SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
- if (DstSize <= SrcSize)
+ if (TypeSize::isKnownLE(DstSize, SrcSize))
report("inserted size must be smaller than total register", MI);
- if (SrcSize + OffsetOp.getImm() > DstSize)
+ if (SrcSize.getKnownMinValue() + OffsetOp.getImm() >
+ DstSize.getKnownMinValue())
report("insert writes past end of register", MI);
break;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 64e8ee76e83915..25686799d377ff 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -580,6 +580,16 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
SplatActions.clampScalar(1, sXLen, sXLen);
+ getActionDefinitionsBuilder(G_INSERT)
+ .customIf(all(typeIsLegalBoolVec(0, BoolVecTys, ST),
+ typeIsLegalBoolVec(1, BoolVecTys, ST)))
+ .customIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+ typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)));
+
+ getActionDefinitionsBuilder(G_EXTRACT)
+ .customIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
+ .customIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST));
+
getLegacyLegalizerInfo().computeTables();
}
@@ -802,6 +812,14 @@ bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
return true;
}
+static LLT getLMUL1Ty(LLT VecTy) {
+ assert(VecTy.getElementType().getSizeInBits() <= 64 &&
+ "Unexpected vector LLT");
+ return LLT::scalable_vector(RISCV::RVVBitsPerBlock /
+ VecTy.getElementType().getSizeInBits(),
+ VecTy.getElementType());
+}
+
/// Return the type of the mask type suitable for masking the provided
/// vector type. This is simply an i1 element type vector of the same
/// (possibly scalable) length.
@@ -858,6 +876,11 @@ buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru,
Unmerge.getReg(1), VL, MIB, MRI);
}
+static MachineInstrBuilder buildVLMax(LLT VecTy, MachineIRBuilder &MIB) {
+ assert(VecTy.isScalableVector() && "Expected scalable vector");
+ return MIB.buildVScale(VecTy, VecTy.getElementCount().getKnownMinValue());
+}
+
// Lower splats of s1 types to G_ICMP. For each mask vector type, we have a
// legal equivalently-sized i8 type, so we can use that as a go-between.
// Splats of s1 types that have constant value can be legalized as VMSET_VL or
@@ -914,6 +937,263 @@ bool RISCVLegalizerInfo::legalizeSplatVector(MachineInstr &MI,
return true;
}
+bool RISCVLegalizerInfo::legalizeInsert(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ assert(MI.getOpcode() == TargetOpcode::G_INSERT);
+
+ MachineRegisterInfo &MRI = *MIB.getMRI();
+
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src1 = MI.getOperand(1).getReg();
+ Register Src2 = MI.getOperand(2).getReg();
+ uint64_t Idx = MI.getOperand(3).getImm();
+
+ LLT LitTy = MRI.getType(Src2);
+ Register BigVec = Src1;
+ Register LitVec = Src2;
+
+ // We don't have the ability to slide mask vectors up indexed by their i1
+ // elements; the smallest we can do is i8. Often we are able to bitcast to
+ // equivalent i8 vectors. Otherwise, we can must zeroextend to equivalent i8
+ // vectors and truncate down after the insert.
+ if (LitTy.getElementType() == LLT::scalar(1) &&
+ (Idx != 0 ||
+ MRI.getVRegDef(BigVec)->getOpcode() != TargetOpcode::G_IMPLICIT_DEF)) {
+ auto BigTyMinElts = BigTy.getElementCount().getKnownMinValue();
+ auto LitTyMinElts = LitTy.getElementCount().getKnownMinValue();
+ if (BigTyMinElts >= 8 && LitTyMinElts >= 8) {
+ assert(Idx % 8 == 0 && "Invalid index");
+ assert(BigTyMinElts % 8 == 0 && LitTyMinElts % 8 == 0 &&
+ "Unexpected mask vector lowering");
+ Idx /= 8;
+ BigTy = LLT::vector(BigTy.getElementCount().divideCoefficientBy(8), 8);
+ LitTy = LLT::vector(LitTy.getElementCount().divideCoefficientBy(8), 8);
+ BigVec = MIB.buildBitcast(BigTy, BigVec).getReg(0);
+ LitVec = MIB.buildBitcast(LitTy, LitVec).getReg(0);
+ } else {
+ // We can't slide this mask vector up indexed by its i1 elements.
+ // This poses a problem when we wish to insert a scalable vector which
+ // can't be re-expressed as a larger type. Just choose the slow path and
+ // extend to a larger type, then truncate back down.
+ LLT ExtBigTy = BigTy.changeElementType(LLT::scalar(8));
+ LLT ExtLitTy = LitTy.changeElementType(LLT::scalar(8));
+ auto BigZExt = MIB.buildZExt(ExtBigTy, BigVec);
+ auto LitZExt = MIB.buildZExt(ExtLitTy, LitVec);
+ auto Insert = MIB.buildInsert(ExtBigTy, BigZExt, LitZExt, Idx);
+ auto SplatZero = MIB.buildConstant(ExtBigTy, 0);
+ MIB.buildICmp(CmpInst::Predicate::ICMP_NE, Dst, Insert, SplatZero);
+ MI.eraseFromParent();
+ return true;
+ }
+ }
+
+ const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
+ MVT LitTyMVT = getMVTForLLT(LitTy);
+ unsigned SubRegIdx, RemIdx;
+ std::tie(SubRegIdx, RemIdx) =
+ RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
+ getMVTForLLT(BigTy), LitTyMVT, Idx, TRI);
+
+ RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(getMVTForLLT(LitTy));
+ bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 ||
+ SubVecLMUL == RISCVII::VLMUL::LMUL_F4 ||
+ SubVecLMUL == RISCVII::VLMUL::LMUL_F8;
+
+ // If the Idx has been completely eliminated and this subvector's size is a
+ // vector register or a multiple thereof, or the surrounding elements are
+ // undef, then this is a subvector insert which naturally aligns to a vector
+ // register. These can easily be handled using subregister manipulation.
+ if (RemIdx == 0 && (!IsSubVecPartReg || MRI.getVRegDef(Src1)->getOpcode() ==
+ TargetOpcode::G_IMPLICIT_DEF))
+ return true;
+
+ // If the subvector is smaller than a vector register, then the insertion
+ // must preserve the undisturbed elements of the register. We do this by
+ // lowering to an EXTRACT_SUBVECTOR grabbing the nearest LMUL=1 vector type
+ // (which resolves to a subregister copy), performing a VSLIDEUP to place the
+ // subvector within the vector register, and an INSERT_SUBVECTOR of that
+ // LMUL=1 type back into the larger vector (resolving to another subregister
+ // operation). See below for how our VSLIDEUP works. We go via a LMUL=1 type
+ // to avoid allocating a large register group to hold our subvector.
+
+ // VSLIDEUP works by leaving elements 0<i<OFFSET undisturbed, elements
+ // OFFSET<=i<VL set to the "subvector" and vl<=i<VLMAX set to the tail policy
+ // (in our case undisturbed). This means we can set up a subvector insertion
+ // where OFFSET is the insertion offset, and the VL is the OFFSET plus the
+ // size of the subvector.
+ const LLT XLenTy(STI.getXLenVT());
+ LLT InterLitTy = BigTy;
+ Register AlignedExtract = Src1;
+ unsigned AlignedIdx = Idx - RemIdx;
+ if (TypeSize::isKnownGT(BigTy.getSizeInBits(),
+ getLMUL1Ty(BigTy).getSizeInBits())) {
+ InterLitTy = getLMUL1Ty(BigTy);
+ // Extract a subvector equal to the nearest full vector register type. This
+ // should resolve to a G_EXTRACT on a subreg.
+ AlignedExtract = MIB.buildExtract(InterLitTy, BigVec, AlignedIdx).getReg(0);
+ }
+
+ auto Insert =
+ MIB.buildInsert(InterLitTy, MIB.buildUndef(InterLitTy), LitVec, 0);
+
+ auto [Mask, VL] = buildDefaultVLOps(BigTy, MIB, MRI);
+
+ ElementCount EndIndex =
+ ElementCount::getScalable(RemIdx) + LitTy.getElementCount();
+ VL = buildVLMax(LitTy, MIB).getReg(0);
+
+ // Use tail agnostic policy if we're inserting over InterLitTy's tail.
+ uint64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+ if (EndIndex == InterLitTy.getElementCount())
+ Policy = RISCVII::TAIL_AGNOSTIC;
+
+ // If we're inserting into the lowest elements, use a tail undisturbed
+ // vmv.v.v.
+ Register Inserted;
+ if (RemIdx == 0) {
+ Inserted = MIB.buildInstr(RISCV::G_VMV_V_V_VL, {InterLitTy},
+ {AlignedExtract, Insert, VL})
+ .getReg(0);
+ } else {
+ auto SlideupAmt = MIB.buildVScale(XLenTy, RemIdx);
+ // Construct the vector length corresponding to RemIdx + length(LitTy).
+ VL = MIB.buildAdd(XLenTy, SlideupAmt, VL).getReg(0);
+ Inserted =
+ MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {InterLitTy},
+ {AlignedExtract, LitVec, SlideupAmt, Mask, VL, Policy})
+ .getReg(0);
+ }
+
+ // If required, insert this subvector back into the correct vector register.
+ // This should resolve to an INSERT_SUBREG instruction.
+ if (TypeSize::isKnownGT(BigTy.getSizeInBits(), InterLitTy.getSizeInBits()))
+ Inserted = MIB.buildInsert(BigTy, BigVec, LitVec, AlignedIdx).getReg(0);
+
+ // We might have bitcast from a mask type: cast back to the original type if
+ // required.
+ MIB.buildBitcast(Dst, Inserted);
+
+ MI.eraseFromParent();
+ return true;
+}
+
+bool RISCVLegalizerInfo::legalizeExtract(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ assert(MI.getOpcode() == TargetOpcode::G_EXTRACT);
+
+ MachineRegisterInfo &MRI = *MIB.getMRI();
+
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ uint64_t Idx = MI.getOperand(2).getImm();
+
+ // Only support vectors using custom legalization
+ LLT LitTy = MRI.getType(Dst);
+ if (LitTy.isScalar())
+ return false;
+
+ LLT BigTy = MRI.getType(Src);
+ Register Vec = Src;
+
+ // We don't have the ability to slide mask vectors down indexed by their i1
+ // elements; the smallest we can do is i8. Often we are able to bitcast to
+ // equivalent i8 vectors.
+ if (LitTy.getElementType() == LLT::scalar(1) && Idx != 0) {
+ auto BigTyMinElts = BigTy.getElementCount().getKnownMinValue();
+ auto LitTyMinElts = LitTy.getElementCount().getKnownMinValue();
+ if (BigTyMinElts >= 8 && LitTyMinElts >= 8) {
+ assert(Idx % 8 == 0 && "Invalid index");
+ assert(BigTyMinElts % 8 == 0 && LitTyMinElts % 8 == 0 &&
+ "Unexpected mask vector lowering");
+ Idx /= 8;
+ BigTy = LLT::vector(BigTy.getElementCount().divideCoefficientBy(8), 8);
+ LitTy = LLT::vector(LitTy.getElementCount().divideCoefficientBy(8), 8);
+ Vec = MIB.buildBitcast(BigTy, Vec).getReg(0);
+ } else {
+ // We can't slide this mask vector up indexed by its i1 elements.
+ // This poses a problem when we wish to insert a scalable vector which
+ // can't be re-expressed as a larger type. Just choose the slow path and
+ // extend to a larger type, then truncate back down.
+ LLT ExtBigTy = BigTy.changeElementType(LLT::scalar(8));
+ LLT ExtLitTy = LitTy.changeElementType(LLT::scalar(8));
+ auto BigZExt = MIB.buildZExt(ExtBigTy, Vec);
+ auto ExtractZExt = MIB.buildExtract(ExtLitTy, BigZExt, Idx);
+ auto SplatZero = MIB.buildSplatVector(
+ ExtLitTy, MIB.buildConstant(ExtLitTy.getElementType(), 0));
+ MIB.buildICmp(CmpInst::Predicate::ICMP_NE, Dst, ExtractZExt, SplatZero);
+ MI.eraseFromParent();
+ return true;
+ }
+ }
+
+ // With an index of 0 this is a cast-like subvector, which can be performed
+ // with subregister operations.
+ if (Idx == 0)
+ return true;
+
+ // extract_subvector scales the index by vscale if the subvector is scalable,
+ // and decomposeSubvectorInsertExtractToSubRegs takes this into account.
+ const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
+ MVT LitTyMVT = getMVTForLLT(LitTy);
+ unsigned SubRegIdx;
+ ElementCount RemIdx;
+ auto Decompose =
+ RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
+ getMVTForLLT(BigTy), LitTyMVT, Idx, TRI);
+ SubRegIdx = Decompose.first;
+ RemIdx = ElementCount::getScalable(Decompose.second);
+
+ // If the Idx has been completely eliminated then this is a subvector extract
+ // which naturally aligns to a vector register. These can easily be handled
+ // using subregister manipulation.
+ // TODO: add tests
+ if (RemIdx.isZero()) {
+ assert(false);
+ return true;
+ }
+
+ // Else LitTy is M1 or smaller and may need to be slid down: if LitTy
+ // was > M1 then the index would need to be a multiple of VLMAX, and so would
+ // divide exactly.
+ assert(
+ RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(LitTyMVT)).second ||
+ RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVII::VLMUL::LMUL_1);
+
+ // If the vector type is an LMUL-group type, extract a subvector equal to the
+ // nearest full vector register type.
+ LLT InterLitTy = BigTy;
+ if (TypeSize::isKnownGT(BigTy.getSizeInBits(),
+ getLMUL1Ty(BigTy).getSizeInBits())) {
+ // If BigTy has an LMUL > 1, then LitTy should have a smaller LMUL, and
+ // we should have successfully decomposed the extract into a subregister.
+ assert(SubRegIdx != RISCV::NoSubRegister);
+ InterLitTy = getLMUL1Ty(BigTy);
+ // TODO: need to make this a G_EXTRACT_SUBREG?
+ Vec = MIB.buildExtract(InterLitTy, Vec, SubRegIdx).getReg(0);
+ }
+
+ // Slide this vector register down by the desired number of elements in order
+ // to place the desired subvector starting at element 0.
+ const LLT XLenTy(STI.getXLenVT());
+ auto SlidedownAmt = MIB.buildVScale(XLenTy, RemIdx.getKnownMinValue());
+ auto [Mask, VL] = buildDefaultVLOps(LitTy, MIB, MRI);
+ uint64_t Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
+ auto Slidedown = MIB.buildInstr(
+ RISCV::G_VSLIDEDOWN_VL, {InterLitTy},
+ {MIB.buildUndef(InterLitTy), Vec, SlidedownAmt, Mask, VL, Policy});
+
+ // Now the vector is in the right position, extract our final subvector. This
+ // should resolve to a COPY.
+ auto Extract = MIB.buildExtract(LitTy, Slidedown, 0);
+
+ // We might have bitcast from a mask type: cast back to the original type if
+ // required.
+ MIB.buildBitcast(Dst, Extract);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool RISCVLegalizerInfo::legalizeCustom(
LegalizerHelper &Helper, MachineInstr &MI,
LostDebugLocObserver &LocObserver) const {
@@ -987,6 +1267,10 @@ bool RISCVLegalizerInfo::legalizeCustom(
case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE:
return legalizeLoadStore(MI, Helper, MIRBuilder);
+ case TargetOpcode::G_INSERT:
+ return legalizeInsert(MI, MIRBuilder);
+ case TargetOpcode::G_EXTRACT:
+ return legalizeExtract(MI, MIRBuilder);
}
llvm_unreachable("expected switch to return");
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 2fc28615e7630d..c71a9158fe2f4a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -48,6 +48,8 @@ class RISCVLegalizerInfo : public LegalizerInfo {
bool legalizeSplatVector(MachineInstr &MI, MachineIRBuilder &MIB) const;
bool legalizeLoadStore(MachineInstr &MI, LegalizerHelper &Helper,
MachineIRBuilder &MIB) const;
+ bool legalizeInsert(MachineInstr &MI, MachineIRBuilder &MIB) const;
+ bool legalizeExtract(MachineInstr &MI, MachineIRBuilder &MIB) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index ba40662c49c1df..4150f2b2c93777 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -41,6 +41,82 @@ def G_VMCLR_VL : RISCVGenericInstruction {
}
def : GINodeEquiv<G_VMCLR_VL, riscv_vmclr_vl>;
+// Pseudo equivalent to a RISCVISD::VFMV_S_F_VL
+def G_VFMV_S_F_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$vec, type1:$scalar, type2:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VFMV_S_F_VL, riscv_vfmv_s_f_vl>;
+
+// Pseudo equivalent to a RISCVISD::VFMV_V_F_VL
+def G_VFMV_V_F_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$vec, type1:$scalar, type2:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VFMV_V_F_VL, riscv_vfmv_v_f_vl>;
+
+// Pseudo equivalent to a RISCVISD::VMV_S_X_VL
+def G_VMV_S_X_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$vec, type1:$scalar, type2:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VMV_S_X_VL, riscv_vmv_s_x_vl>;
+
+// Pseudo equivalent to a RISCVISD::VMV_V_X_VL
+def G_VMV_V_X_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$vec, type1:$scalar, type2:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VMV_V_X_VL, riscv_vmv_v_x_vl>;
+
+// Pseudo equivalent to a RISCVISD::VMV_V_V_VL
+def G_VMV_V_V_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$vec, type2:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VMV_V_V_VL, riscv_vmv_v_v_vl>;
+
+// This instruction is a vector move instruction where the type of the element
+// can be either a integer or a floating point but the registerbank information
+// is not yet available to decide between G_VMV_V_X and G_VFMV_V_F.
+def G_VEC_MOVE_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$ve...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/108220
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