[llvm] Prefer isSafeToSpeculativelyExecute to div/rem (PR #91157)

Rose Silicon via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 10 06:15:26 PDT 2024

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https://github.com/RSilicon closed https://github.com/llvm/llvm-project/pull/91157

Previous message: [llvm] [InstCombine] Allow overflowing selects to work on commutative arguments (PR #90812)
Next message: [llvm] [SelectionDAG] Use ZERO_EXTEND_VECTOR_INREG for vectors (PR #92048)
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