[llvm] [RISCV][MI] Support partial spill/reload for vector registers (PR #105661)

[Luke Lau via llvm-commits]

lukel97 wrote:

> I have a rough try before, I don't remember the details now but I met a problem that the root cause is because we can't use the high part of fractional registers, which is like X86‘s (for example, EAX | AX | AH/AL). The subreg indexes/RegisterClass should be modeled separately with `CoveredBySubRegs`.

I'm also now thinking that subregisters would only allow us to spill in terms of fractional LMULs. I think this approach of controlling it with VL might help in cases where VLEN is much bigger than DLEN.

https://github.com/llvm/llvm-project/pull/105661