[llvm] [RISCV][MI] Support partial spill/reload for vector registers (PR #105661)

[Luke Lau via llvm-commits]

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@@ -126,6 +126,10 @@ enum {
 
   ActiveElementsAffectResultShift = TargetOverlapConstraintTypeShift + 2,
   ActiveElementsAffectResultMask = 1ULL << ActiveElementsAffectResultShift,
+
+  // Indicates whether the instruction produces widened result.
+  IsWidenShift = ActiveElementsAffectResultShift + 1,
+  IsWidenMask = 1 << IsWidenShift,
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lukel97 wrote:

Can this be replaced with DestEEW after #105945?

https://github.com/llvm/llvm-project/pull/105661