[llvm] [RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (PR #107361)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 00:39:00 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
There is no Fmv with Zfinx.
---
Patch is 111.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/107361.diff
13 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4-3)
- (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+18-18)
- (modified) llvm/test/CodeGen/RISCV/double-imm.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/double-intrinsics.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/double-round-conv.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/float-convert.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/float-round-conv-sat.ll (+24-24)
- (modified) llvm/test/CodeGen/RISCV/half-arith.ll (+12-29)
- (modified) llvm/test/CodeGen/RISCV/half-convert.ll (+116-116)
- (modified) llvm/test/CodeGen/RISCV/half-imm.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/half-intrinsics.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/half-round-conv-sat.ll (+132-132)
- (modified) llvm/test/CodeGen/RISCV/half-round-conv.ll (+150-150)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d400b2ea1ca2ca..cbc57717713f3f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2288,10 +2288,11 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
return true;
// Building an integer and then converting requires a fmv at the end of
- // the integer sequence.
+ // the integer sequence. The fmv is not requires for Zfinx.
+ const int FmvCost = Subtarget.hasStdExtZfinx() ? 0 : 1;
const int Cost =
- 1 + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(), Subtarget.getXLen(),
- Subtarget);
+ FmvCost + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(),
+ Subtarget.getXLen(), Subtarget);
return Cost <= FPImmCost;
}
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 2e2e1b924cf009..ef2d8e7627be54 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -1668,16 +1668,16 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
-; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
-; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
-; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
-; RV64IZFINXZDINX-NEXT: neg a3, a3
-; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
+; RV64IZFINXZDINX-NEXT: neg a1, a1
+; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
+; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_0)(a2)
+; RV64IZFINXZDINX-NEXT: li a3, -505
+; RV64IZFINXZDINX-NEXT: slli a3, a3, 53
+; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a3
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
-; RV64IZFINXZDINX-NEXT: and a0, a3, a0
+; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -2043,16 +2043,16 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI30_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
-; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
-; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
-; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
-; RV64IZFINXZDINX-NEXT: neg a3, a3
-; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
+; RV64IZFINXZDINX-NEXT: neg a1, a1
+; RV64IZFINXZDINX-NEXT: li a2, -509
+; RV64IZFINXZDINX-NEXT: slli a2, a2, 53
+; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV64IZFINXZDINX-NEXT: lui a2, 65919
+; RV64IZFINXZDINX-NEXT: slli a2, a2, 34
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
-; RV64IZFINXZDINX-NEXT: and a0, a3, a0
+; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
@@ -2234,9 +2234,9 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI32_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI32_0)(a1)
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
+; RV64IZFINXZDINX-NEXT: lui a1, 131967
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 33
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 74d4acc4f23f8c..827f034f143fb5 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -62,8 +62,8 @@ define double @double_imm_op(double %a) nounwind {
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
; CHECKRV64ZDINX: # %bb.0:
-; CHECKRV64ZDINX-NEXT: lui a1, %hi(.LCPI1_0)
-; CHECKRV64ZDINX-NEXT: ld a1, %lo(.LCPI1_0)(a1)
+; CHECKRV64ZDINX-NEXT: li a1, 1023
+; CHECKRV64ZDINX-NEXT: slli a1, a1, 52
; CHECKRV64ZDINX-NEXT: fadd.d a0, a0, a1
; CHECKRV64ZDINX-NEXT: ret
%1 = fadd double %a, 1.0
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index eef48d1eafbfed..94b3b1f1b199c2 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -869,8 +869,8 @@ define double @floor_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: floor_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI17_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB17_2
@@ -934,8 +934,8 @@ define double @ceil_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: ceil_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI18_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI18_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2
@@ -999,8 +999,8 @@ define double @trunc_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: trunc_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI19_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2
@@ -1064,8 +1064,8 @@ define double @rint_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: rint_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI20_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI20_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2
@@ -1170,8 +1170,8 @@ define double @round_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: round_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI22_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI22_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB22_2
@@ -1235,8 +1235,8 @@ define double @roundeven_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: roundeven_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI23_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv.ll b/llvm/test/CodeGen/RISCV/double-round-conv.ll
index d84d80a4a10e92..12f025c65f36ae 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv.ll
@@ -1130,8 +1130,8 @@ define double @test_floor_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_floor_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI40_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI40_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB40_2
@@ -1177,8 +1177,8 @@ define double @test_ceil_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_ceil_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI41_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI41_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB41_2
@@ -1224,8 +1224,8 @@ define double @test_trunc_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_trunc_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI42_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI42_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB42_2
@@ -1271,8 +1271,8 @@ define double @test_round_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_round_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI43_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI43_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB43_2
@@ -1318,8 +1318,8 @@ define double @test_roundeven_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_roundeven_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI44_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI44_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 805ddee4ac3f6f..031976b4fa2b21 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -682,8 +682,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: # %bb.1: # %start
; RV32IZFINX-NEXT: mv a2, a1
; RV32IZFINX-NEXT: .LBB12_2: # %start
-; RV32IZFINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV32IZFINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
+; RV32IZFINX-NEXT: lui a1, 389120
+; RV32IZFINX-NEXT: addi a1, a1, -1
; RV32IZFINX-NEXT: flt.s a3, a1, s0
; RV32IZFINX-NEXT: beqz a3, .LBB12_4
; RV32IZFINX-NEXT: # %bb.3:
@@ -910,9 +910,9 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1445,11 +1445,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
; RV32IZFINX-NEXT: feq.s a1, a0, a0
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV32IZFINX-NEXT: neg a1, a1
-; RV32IZFINX-NEXT: lui a3, 815104
-; RV32IZFINX-NEXT: fmax.s a0, a0, a3
+; RV32IZFINX-NEXT: lui a2, 815104
+; RV32IZFINX-NEXT: fmax.s a0, a0, a2
+; RV32IZFINX-NEXT: lui a2, 290816
+; RV32IZFINX-NEXT: addi a2, a2, -512
; RV32IZFINX-NEXT: fmin.s a0, a0, a2
; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZFINX-NEXT: and a0, a1, a0
@@ -1458,11 +1458,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: feq.s a1, a0, a0
-; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
-; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV64IZFINX-NEXT: neg a1, a1
-; RV64IZFINX-NEXT: lui a3, 815104
-; RV64IZFINX-NEXT: fmax.s a0, a0, a3
+; RV64IZFINX-NEXT: lui a2, 815104
+; RV64IZFINX-NEXT: fmax.s a0, a0, a2
+; RV64IZFINX-NEXT: lui a2, 290816
+; RV64IZFINX-NEXT: addiw a2, a2, -512
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZFINX-NEXT: and a0, a1, a0
@@ -1622,18 +1622,18 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
;
; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
-; RV32IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV32IZFINX-NEXT: fmax.s a0, a0, zero
+; RV32IZFINX-NEXT: lui a1, 292864
+; RV32IZFINX-NEXT: addi a1, a1, -256
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
-; RV64IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV64IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV64IZFINX-NEXT: fmax.s a0, a0, zero
+; RV64IZFINX-NEXT: lui a1, 292864
+; RV64IZFINX-NEXT: addiw a1, a1, -256
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZFINX-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
index 5e99c7eb905628..42ac20286a8920 100644
--- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
@@ -112,9 +112,9 @@ define i64 @test_floor_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -241,9 +241,9 @@ define i64 @test_floor_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI3_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI3_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -372,9 +372,9 @@ define i64 @test_ceil_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -501,9 +501,9 @@ define i64 @test_ceil_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI7_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI7_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -632,9 +632,9 @@ define i64 @test_trunc_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -761,9 +761,9 @@ define i64 @test_trunc_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI11_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI11_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -892,9 +892,9 @@ define i64 @test_round_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1021,9 +1021,9 @@ define i64 @test_round_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI15_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI15_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1152,9 +1152,9 @@ define i64 @test_roundeven_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1281,9 +1281,9 @@ define i64 @test_roundeven_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI19_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI19_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1412,9 +1412,9 @@ define i64 @test_rint_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1541,9 +1541,9 @@ define i64 @test_rint_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI23_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index f8522b09970bf9..b033c75eeadd8b 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -2910,35 +2910,18 @@ define half @fsgnjx_f16(half %x, half %y) nounwind {
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV64IZFHMIN-NEXT: ret
;
-; RV32IZHINXMIN-LABEL: fsgnjx_f16:
-; RV32IZHINXMIN: # %bb.0:
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZHINXMIN-NEXT: lh a2, %lo(.LCPI23_0)(a2)
-; RV32IZHINXMIN-NEXT: lui a3, 1048568
-; RV32IZHINXMIN-NEXT: and a0, a0...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/107361
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