[llvm] [RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (PR #107361)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 00:38:28 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/107361
There is no Fmv with Zfinx.
>From 5af7a8e5962333130f9c8f1302fecad63809c7c2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Sep 2024 00:34:25 -0700
Subject: [PATCH] [RISCV] Don't cost Fmv for Zfinx in isFPImmLegal.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +-
llvm/test/CodeGen/RISCV/double-convert.ll | 36 +--
llvm/test/CodeGen/RISCV/double-imm.ll | 4 +-
llvm/test/CodeGen/RISCV/double-intrinsics.ll | 24 +-
llvm/test/CodeGen/RISCV/double-round-conv.ll | 20 +-
llvm/test/CodeGen/RISCV/float-convert.ll | 32 +-
.../CodeGen/RISCV/float-round-conv-sat.ll | 48 +--
llvm/test/CodeGen/RISCV/half-arith.ll | 41 +--
llvm/test/CodeGen/RISCV/half-convert.ll | 232 +++++++-------
llvm/test/CodeGen/RISCV/half-imm.ll | 8 +-
llvm/test/CodeGen/RISCV/half-intrinsics.ll | 24 +-
.../test/CodeGen/RISCV/half-round-conv-sat.ll | 264 +++++++--------
llvm/test/CodeGen/RISCV/half-round-conv.ll | 300 +++++++++---------
13 files changed, 512 insertions(+), 528 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d400b2ea1ca2ca..cbc57717713f3f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2288,10 +2288,11 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
return true;
// Building an integer and then converting requires a fmv at the end of
- // the integer sequence.
+ // the integer sequence. The fmv is not requires for Zfinx.
+ const int FmvCost = Subtarget.hasStdExtZfinx() ? 0 : 1;
const int Cost =
- 1 + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(), Subtarget.getXLen(),
- Subtarget);
+ FmvCost + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(),
+ Subtarget.getXLen(), Subtarget);
return Cost <= FPImmCost;
}
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 2e2e1b924cf009..ef2d8e7627be54 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -1668,16 +1668,16 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
-; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
-; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
-; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
-; RV64IZFINXZDINX-NEXT: neg a3, a3
-; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
+; RV64IZFINXZDINX-NEXT: neg a1, a1
+; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
+; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_0)(a2)
+; RV64IZFINXZDINX-NEXT: li a3, -505
+; RV64IZFINXZDINX-NEXT: slli a3, a3, 53
+; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a3
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
-; RV64IZFINXZDINX-NEXT: and a0, a3, a0
+; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -2043,16 +2043,16 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI30_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
-; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
-; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
-; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
-; RV64IZFINXZDINX-NEXT: neg a3, a3
-; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
+; RV64IZFINXZDINX-NEXT: neg a1, a1
+; RV64IZFINXZDINX-NEXT: li a2, -509
+; RV64IZFINXZDINX-NEXT: slli a2, a2, 53
+; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV64IZFINXZDINX-NEXT: lui a2, 65919
+; RV64IZFINXZDINX-NEXT: slli a2, a2, 34
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
-; RV64IZFINXZDINX-NEXT: and a0, a3, a0
+; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
@@ -2234,9 +2234,9 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI32_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI32_0)(a1)
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
+; RV64IZFINXZDINX-NEXT: lui a1, 131967
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 33
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 74d4acc4f23f8c..827f034f143fb5 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -62,8 +62,8 @@ define double @double_imm_op(double %a) nounwind {
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
; CHECKRV64ZDINX: # %bb.0:
-; CHECKRV64ZDINX-NEXT: lui a1, %hi(.LCPI1_0)
-; CHECKRV64ZDINX-NEXT: ld a1, %lo(.LCPI1_0)(a1)
+; CHECKRV64ZDINX-NEXT: li a1, 1023
+; CHECKRV64ZDINX-NEXT: slli a1, a1, 52
; CHECKRV64ZDINX-NEXT: fadd.d a0, a0, a1
; CHECKRV64ZDINX-NEXT: ret
%1 = fadd double %a, 1.0
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index eef48d1eafbfed..94b3b1f1b199c2 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -869,8 +869,8 @@ define double @floor_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: floor_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI17_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB17_2
@@ -934,8 +934,8 @@ define double @ceil_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: ceil_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI18_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI18_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2
@@ -999,8 +999,8 @@ define double @trunc_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: trunc_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI19_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2
@@ -1064,8 +1064,8 @@ define double @rint_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: rint_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI20_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI20_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2
@@ -1170,8 +1170,8 @@ define double @round_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: round_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI22_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI22_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB22_2
@@ -1235,8 +1235,8 @@ define double @roundeven_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: roundeven_f64:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI23_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv.ll b/llvm/test/CodeGen/RISCV/double-round-conv.ll
index d84d80a4a10e92..12f025c65f36ae 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv.ll
@@ -1130,8 +1130,8 @@ define double @test_floor_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_floor_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI40_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI40_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB40_2
@@ -1177,8 +1177,8 @@ define double @test_ceil_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_ceil_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI41_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI41_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB41_2
@@ -1224,8 +1224,8 @@ define double @test_trunc_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_trunc_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI42_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI42_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB42_2
@@ -1271,8 +1271,8 @@ define double @test_round_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_round_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI43_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI43_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB43_2
@@ -1318,8 +1318,8 @@ define double @test_roundeven_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_roundeven_double:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI44_0)
-; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI44_0)(a1)
+; RV64IZFINXZDINX-NEXT: li a1, 1075
+; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 805ddee4ac3f6f..031976b4fa2b21 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -682,8 +682,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: # %bb.1: # %start
; RV32IZFINX-NEXT: mv a2, a1
; RV32IZFINX-NEXT: .LBB12_2: # %start
-; RV32IZFINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV32IZFINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
+; RV32IZFINX-NEXT: lui a1, 389120
+; RV32IZFINX-NEXT: addi a1, a1, -1
; RV32IZFINX-NEXT: flt.s a3, a1, s0
; RV32IZFINX-NEXT: beqz a3, .LBB12_4
; RV32IZFINX-NEXT: # %bb.3:
@@ -910,9 +910,9 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1445,11 +1445,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
; RV32IZFINX-NEXT: feq.s a1, a0, a0
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV32IZFINX-NEXT: neg a1, a1
-; RV32IZFINX-NEXT: lui a3, 815104
-; RV32IZFINX-NEXT: fmax.s a0, a0, a3
+; RV32IZFINX-NEXT: lui a2, 815104
+; RV32IZFINX-NEXT: fmax.s a0, a0, a2
+; RV32IZFINX-NEXT: lui a2, 290816
+; RV32IZFINX-NEXT: addi a2, a2, -512
; RV32IZFINX-NEXT: fmin.s a0, a0, a2
; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZFINX-NEXT: and a0, a1, a0
@@ -1458,11 +1458,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: feq.s a1, a0, a0
-; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
-; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV64IZFINX-NEXT: neg a1, a1
-; RV64IZFINX-NEXT: lui a3, 815104
-; RV64IZFINX-NEXT: fmax.s a0, a0, a3
+; RV64IZFINX-NEXT: lui a2, 815104
+; RV64IZFINX-NEXT: fmax.s a0, a0, a2
+; RV64IZFINX-NEXT: lui a2, 290816
+; RV64IZFINX-NEXT: addiw a2, a2, -512
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZFINX-NEXT: and a0, a1, a0
@@ -1622,18 +1622,18 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
;
; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
-; RV32IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV32IZFINX-NEXT: fmax.s a0, a0, zero
+; RV32IZFINX-NEXT: lui a1, 292864
+; RV32IZFINX-NEXT: addi a1, a1, -256
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
-; RV64IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
-; RV64IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV64IZFINX-NEXT: fmax.s a0, a0, zero
+; RV64IZFINX-NEXT: lui a1, 292864
+; RV64IZFINX-NEXT: addiw a1, a1, -256
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZFINX-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
index 5e99c7eb905628..42ac20286a8920 100644
--- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
@@ -112,9 +112,9 @@ define i64 @test_floor_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -241,9 +241,9 @@ define i64 @test_floor_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI3_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI3_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -372,9 +372,9 @@ define i64 @test_ceil_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -501,9 +501,9 @@ define i64 @test_ceil_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI7_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI7_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -632,9 +632,9 @@ define i64 @test_trunc_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -761,9 +761,9 @@ define i64 @test_trunc_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI11_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI11_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -892,9 +892,9 @@ define i64 @test_round_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1021,9 +1021,9 @@ define i64 @test_round_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI15_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI15_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1152,9 +1152,9 @@ define i64 @test_roundeven_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1281,9 +1281,9 @@ define i64 @test_roundeven_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI19_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI19_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1412,9 +1412,9 @@ define i64 @test_rint_si64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s2, s1
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixsfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2)
; RV32IZFINX-NEXT: and a0, s2, a0
+; RV32IZFINX-NEXT: lui a2, 389120
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a4, a2, s0
; RV32IZFINX-NEXT: neg a2, a4
; RV32IZFINX-NEXT: or a0, a2, a0
@@ -1541,9 +1541,9 @@ define i64 @test_rint_ui64(float %x) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
-; RV32IZFINX-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZFINX-NEXT: lw a2, %lo(.LCPI23_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
+; RV32IZFINX-NEXT: lui a2, 391168
+; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index f8522b09970bf9..b033c75eeadd8b 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -2910,35 +2910,18 @@ define half @fsgnjx_f16(half %x, half %y) nounwind {
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV64IZFHMIN-NEXT: ret
;
-; RV32IZHINXMIN-LABEL: fsgnjx_f16:
-; RV32IZHINXMIN: # %bb.0:
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZHINXMIN-NEXT: lh a2, %lo(.LCPI23_0)(a2)
-; RV32IZHINXMIN-NEXT: lui a3, 1048568
-; RV32IZHINXMIN-NEXT: and a0, a0, a3
-; RV32IZHINXMIN-NEXT: slli a2, a2, 17
-; RV32IZHINXMIN-NEXT: srli a2, a2, 17
-; RV32IZHINXMIN-NEXT: or a0, a2, a0
-; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
-; RV32IZHINXMIN-NEXT: fmul.s a0, a0, a1
-; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: ret
-;
-; RV64IZHINXMIN-LABEL: fsgnjx_f16:
-; RV64IZHINXMIN: # %bb.0:
-; RV64IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
-; RV64IZHINXMIN-NEXT: lh a2, %lo(.LCPI23_0)(a2)
-; RV64IZHINXMIN-NEXT: lui a3, 1048568
-; RV64IZHINXMIN-NEXT: and a0, a0, a3
-; RV64IZHINXMIN-NEXT: slli a2, a2, 49
-; RV64IZHINXMIN-NEXT: srli a2, a2, 49
-; RV64IZHINXMIN-NEXT: or a0, a2, a0
-; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
-; RV64IZHINXMIN-NEXT: fmul.s a0, a0, a1
-; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV64IZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fsgnjx_f16:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: lui a2, 1048568
+; CHECKIZHINXMIN-NEXT: and a0, a0, a2
+; CHECKIZHINXMIN-NEXT: li a2, 15
+; CHECKIZHINXMIN-NEXT: slli a2, a2, 10
+; CHECKIZHINXMIN-NEXT: or a0, a0, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%z = call half @llvm.copysign.f16(half 1.0, half %x)
%mul = fmul half %z, %y
ret half %mul
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index bc1a6520610206..32f7dfaee8837c 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -255,11 +255,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZHINX: # %bb.0: # %start
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZHINX-NEXT: feq.s a1, a0, a0
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZHINX-NEXT: neg a1, a1
-; RV32IZHINX-NEXT: lui a3, 815104
-; RV32IZHINX-NEXT: fmax.s a0, a0, a3
+; RV32IZHINX-NEXT: lui a2, 815104
+; RV32IZHINX-NEXT: fmax.s a0, a0, a2
+; RV32IZHINX-NEXT: lui a2, 290816
+; RV32IZHINX-NEXT: addi a2, a2, -512
; RV32IZHINX-NEXT: fmin.s a0, a0, a2
; RV32IZHINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINX-NEXT: and a0, a1, a0
@@ -269,11 +269,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZHINX: # %bb.0: # %start
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: feq.s a1, a0, a0
-; RV64IZHINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV64IZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV64IZHINX-NEXT: neg a1, a1
-; RV64IZHINX-NEXT: lui a3, 815104
-; RV64IZHINX-NEXT: fmax.s a0, a0, a3
+; RV64IZHINX-NEXT: lui a2, 815104
+; RV64IZHINX-NEXT: fmax.s a0, a0, a2
+; RV64IZHINX-NEXT: lui a2, 290816
+; RV64IZHINX-NEXT: addiw a2, a2, -512
; RV64IZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZHINX-NEXT: and a0, a1, a0
@@ -283,11 +283,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZDINXZHINX: # %bb.0: # %start
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINX-NEXT: feq.s a1, a0, a0
-; RV32IZDINXZHINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZDINXZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZDINXZHINX-NEXT: neg a1, a1
-; RV32IZDINXZHINX-NEXT: lui a3, 815104
-; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, a3
+; RV32IZDINXZHINX-NEXT: lui a2, 815104
+; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT: lui a2, 290816
+; RV32IZDINXZHINX-NEXT: addi a2, a2, -512
; RV32IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV32IZDINXZHINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZDINXZHINX-NEXT: and a0, a1, a0
@@ -297,11 +297,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZDINXZHINX: # %bb.0: # %start
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: feq.s a1, a0, a0
-; RV64IZDINXZHINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV64IZDINXZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV64IZDINXZHINX-NEXT: neg a1, a1
-; RV64IZDINXZHINX-NEXT: lui a3, 815104
-; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a3
+; RV64IZDINXZHINX-NEXT: lui a2, 815104
+; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a2
+; RV64IZDINXZHINX-NEXT: lui a2, 290816
+; RV64IZDINXZHINX-NEXT: addiw a2, a2, -512
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
@@ -505,11 +505,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK32-IZHINXMIN: # %bb.0: # %start
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK32-IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
-; CHECK32-IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK32-IZHINXMIN-NEXT: neg a1, a1
-; CHECK32-IZHINXMIN-NEXT: lui a3, 815104
-; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK32-IZHINXMIN-NEXT: lui a2, 815104
+; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT: lui a2, 290816
+; CHECK32-IZHINXMIN-NEXT: addi a2, a2, -512
; CHECK32-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: and a0, a1, a0
@@ -519,11 +519,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZHINXMIN: # %bb.0: # %start
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK64-IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
-; CHECK64-IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK64-IZHINXMIN-NEXT: neg a1, a1
-; CHECK64-IZHINXMIN-NEXT: lui a3, 815104
-; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK64-IZHINXMIN-NEXT: lui a2, 815104
+; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK64-IZHINXMIN-NEXT: lui a2, 290816
+; CHECK64-IZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
@@ -533,11 +533,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK32-IZDINXZHINXMIN-NEXT: neg a1, a1
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a3, 815104
-; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, 815104
+; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, 290816
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a2, a2, -512
; CHECK32-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, a1, a0
@@ -547,11 +547,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
-; CHECK64-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK64-IZDINXZHINXMIN-NEXT: neg a1, a1
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a3, 815104
-; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 815104
+; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 290816
+; CHECK64-IZDINXZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
@@ -755,40 +755,40 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_ui_h_sat:
; RV32IZHINX: # %bb.0: # %start
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32IZHINX-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZHINX-NEXT: fmax.s a0, a0, zero
+; RV32IZHINX-NEXT: lui a1, 292864
+; RV32IZHINX-NEXT: addi a1, a1, -256
; RV32IZHINX-NEXT: fmin.s a0, a0, a1
; RV32IZHINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_ui_h_sat:
; RV64IZHINX: # %bb.0: # %start
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV64IZHINX-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: fmax.s a0, a0, zero
+; RV64IZHINX-NEXT: lui a1, 292864
+; RV64IZHINX-NEXT: addiw a1, a1, -256
; RV64IZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_ui_h_sat:
; RV32IZDINXZHINX: # %bb.0: # %start
-; RV32IZDINXZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32IZDINXZHINX-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, zero
+; RV32IZDINXZHINX-NEXT: lui a1, 292864
+; RV32IZDINXZHINX-NEXT: addi a1, a1, -256
; RV32IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV32IZDINXZHINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_ui_h_sat:
; RV64IZDINXZHINX: # %bb.0: # %start
-; RV64IZDINXZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV64IZDINXZHINX-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, zero
+; RV64IZDINXZHINX-NEXT: lui a1, 292864
+; RV64IZDINXZHINX-NEXT: addiw a1, a1, -256
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZDINXZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
@@ -955,40 +955,40 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h_sat:
; CHECK32-IZHINXMIN: # %bb.0: # %start
-; CHECK32-IZHINXMIN-NEXT: lui a1, %hi(.LCPI3_0)
-; CHECK32-IZHINXMIN-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK32-IZHINXMIN-NEXT: lui a1, 292864
+; CHECK32-IZHINXMIN-NEXT: addi a1, a1, -256
; CHECK32-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h_sat:
; CHECK64-IZHINXMIN: # %bb.0: # %start
-; CHECK64-IZHINXMIN-NEXT: lui a1, %hi(.LCPI3_0)
-; CHECK64-IZHINXMIN-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK64-IZHINXMIN-NEXT: lui a1, 292864
+; CHECK64-IZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h_sat:
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %start
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI3_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, 292864
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a1, a1, -256
; CHECK32-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h_sat:
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI3_0)
-; CHECK64-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI3_0)(a1)
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 292864
+; CHECK64-IZDINXZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
@@ -2248,10 +2248,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IZHINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI10_0)
-; RV32IZHINX-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; RV32IZHINX-NEXT: fcvt.s.h s0, a0
-; RV32IZHINX-NEXT: flt.s s1, a1, s0
+; RV32IZHINX-NEXT: lui a0, 389120
+; RV32IZHINX-NEXT: addi a0, a0, -1
+; RV32IZHINX-NEXT: flt.s s1, a0, s0
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: lui a0, 913408
; RV32IZHINX-NEXT: fle.s s3, a0, s0
@@ -2301,10 +2301,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IZDINXZHINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZDINXZHINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZDINXZHINX-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: lui a1, %hi(.LCPI10_0)
-; RV32IZDINXZHINX-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; RV32IZDINXZHINX-NEXT: fcvt.s.h s0, a0
-; RV32IZDINXZHINX-NEXT: flt.s s1, a1, s0
+; RV32IZDINXZHINX-NEXT: lui a0, 389120
+; RV32IZDINXZHINX-NEXT: addi a0, a0, -1
+; RV32IZDINXZHINX-NEXT: flt.s s1, a0, s0
; RV32IZDINXZHINX-NEXT: neg s2, s1
; RV32IZDINXZHINX-NEXT: lui a0, 913408
; RV32IZDINXZHINX-NEXT: fle.s s3, a0, s0
@@ -2651,10 +2651,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; CHECK32-IZHINXMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; CHECK32-IZHINXMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; CHECK32-IZHINXMIN-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: lui a1, %hi(.LCPI10_0)
-; CHECK32-IZHINXMIN-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h s0, a0
-; CHECK32-IZHINXMIN-NEXT: flt.s s1, a1, s0
+; CHECK32-IZHINXMIN-NEXT: lui a0, 389120
+; CHECK32-IZHINXMIN-NEXT: addi a0, a0, -1
+; CHECK32-IZHINXMIN-NEXT: flt.s s1, a0, s0
; CHECK32-IZHINXMIN-NEXT: neg s2, s1
; CHECK32-IZHINXMIN-NEXT: lui a0, 913408
; CHECK32-IZHINXMIN-NEXT: fle.s s3, a0, s0
@@ -2705,10 +2705,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; CHECK32-IZDINXZHINXMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; CHECK32-IZDINXZHINXMIN-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI10_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h s0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: flt.s s1, a1, s0
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a0, 389120
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, a0, -1
+; CHECK32-IZDINXZHINXMIN-NEXT: flt.s s1, a0, s0
; CHECK32-IZDINXZHINXMIN-NEXT: neg s2, s1
; CHECK32-IZDINXZHINXMIN-NEXT: lui a0, 913408
; CHECK32-IZDINXZHINXMIN-NEXT: fle.s s3, a0, s0
@@ -3000,9 +3000,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV32IZHINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
+; RV32IZHINX-NEXT: lui a1, 391168
+; RV32IZHINX-NEXT: addi a1, a1, -1
; RV32IZHINX-NEXT: flt.s a1, a1, a0
; RV32IZHINX-NEXT: neg s0, a1
; RV32IZHINX-NEXT: fle.s a1, zero, a0
@@ -3033,9 +3033,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZDINXZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZDINXZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV32IZDINXZHINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT: lui a1, 391168
+; RV32IZDINXZHINX-NEXT: addi a1, a1, -1
; RV32IZDINXZHINX-NEXT: flt.s a1, a1, a0
; RV32IZDINXZHINX-NEXT: neg s0, a1
; RV32IZDINXZHINX-NEXT: fle.s a1, zero, a0
@@ -3245,9 +3245,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK32-IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK32-IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: lui a1, %hi(.LCPI12_0)
-; CHECK32-IZHINXMIN-NEXT: lw a1, %lo(.LCPI12_0)(a1)
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT: lui a1, 391168
+; CHECK32-IZHINXMIN-NEXT: addi a1, a1, -1
; CHECK32-IZHINXMIN-NEXT: flt.s a1, a1, a0
; CHECK32-IZHINXMIN-NEXT: neg s0, a1
; CHECK32-IZHINXMIN-NEXT: fle.s a1, zero, a0
@@ -3279,9 +3279,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK32-IZDINXZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK32-IZDINXZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI12_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI12_0)(a1)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, 391168
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a1, a1, -1
; CHECK32-IZDINXZHINXMIN-NEXT: flt.s a1, a1, a0
; CHECK32-IZDINXZHINXMIN-NEXT: neg s0, a1
; CHECK32-IZDINXZHINXMIN-NEXT: fle.s a1, zero, a0
@@ -6373,11 +6373,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZHINX: # %bb.0: # %start
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZHINX-NEXT: feq.s a1, a0, a0
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI32_0)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV32IZHINX-NEXT: neg a1, a1
-; RV32IZHINX-NEXT: lui a3, 815104
-; RV32IZHINX-NEXT: fmax.s a0, a0, a3
+; RV32IZHINX-NEXT: lui a2, 815104
+; RV32IZHINX-NEXT: fmax.s a0, a0, a2
+; RV32IZHINX-NEXT: lui a2, 290816
+; RV32IZHINX-NEXT: addi a2, a2, -512
; RV32IZHINX-NEXT: fmin.s a0, a0, a2
; RV32IZHINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINX-NEXT: and a0, a1, a0
@@ -6387,11 +6387,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZHINX: # %bb.0: # %start
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: feq.s a1, a0, a0
-; RV64IZHINX-NEXT: lui a2, %hi(.LCPI32_0)
-; RV64IZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV64IZHINX-NEXT: neg a1, a1
-; RV64IZHINX-NEXT: lui a3, 815104
-; RV64IZHINX-NEXT: fmax.s a0, a0, a3
+; RV64IZHINX-NEXT: lui a2, 815104
+; RV64IZHINX-NEXT: fmax.s a0, a0, a2
+; RV64IZHINX-NEXT: lui a2, 290816
+; RV64IZHINX-NEXT: addiw a2, a2, -512
; RV64IZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZHINX-NEXT: and a0, a1, a0
@@ -6401,11 +6401,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZDINXZHINX: # %bb.0: # %start
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINX-NEXT: feq.s a1, a0, a0
-; RV32IZDINXZHINX-NEXT: lui a2, %hi(.LCPI32_0)
-; RV32IZDINXZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV32IZDINXZHINX-NEXT: neg a1, a1
-; RV32IZDINXZHINX-NEXT: lui a3, 815104
-; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, a3
+; RV32IZDINXZHINX-NEXT: lui a2, 815104
+; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT: lui a2, 290816
+; RV32IZDINXZHINX-NEXT: addi a2, a2, -512
; RV32IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV32IZDINXZHINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZDINXZHINX-NEXT: and a0, a1, a0
@@ -6415,11 +6415,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZDINXZHINX: # %bb.0: # %start
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: feq.s a1, a0, a0
-; RV64IZDINXZHINX-NEXT: lui a2, %hi(.LCPI32_0)
-; RV64IZDINXZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV64IZDINXZHINX-NEXT: neg a1, a1
-; RV64IZDINXZHINX-NEXT: lui a3, 815104
-; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a3
+; RV64IZDINXZHINX-NEXT: lui a2, 815104
+; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a2
+; RV64IZDINXZHINX-NEXT: lui a2, 290816
+; RV64IZDINXZHINX-NEXT: addiw a2, a2, -512
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
@@ -6627,11 +6627,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK32-IZHINXMIN: # %bb.0: # %start
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK32-IZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
-; CHECK32-IZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK32-IZHINXMIN-NEXT: neg a1, a1
-; CHECK32-IZHINXMIN-NEXT: lui a3, 815104
-; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK32-IZHINXMIN-NEXT: lui a2, 815104
+; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT: lui a2, 290816
+; CHECK32-IZHINXMIN-NEXT: addi a2, a2, -512
; CHECK32-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: and a0, a1, a0
@@ -6641,11 +6641,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZHINXMIN: # %bb.0: # %start
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK64-IZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
-; CHECK64-IZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK64-IZHINXMIN-NEXT: neg a1, a1
-; CHECK64-IZHINXMIN-NEXT: lui a3, 815104
-; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK64-IZHINXMIN-NEXT: lui a2, 815104
+; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK64-IZHINXMIN-NEXT: lui a2, 290816
+; CHECK64-IZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
@@ -6655,11 +6655,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK32-IZDINXZHINXMIN-NEXT: neg a1, a1
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a3, 815104
-; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, 815104
+; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, 290816
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a2, a2, -512
; CHECK32-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, a1, a0
@@ -6669,11 +6669,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
-; CHECK64-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK64-IZDINXZHINXMIN-NEXT: neg a1, a1
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a3, 815104
-; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 815104
+; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a2
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 290816
+; CHECK64-IZDINXZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
@@ -6876,40 +6876,40 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZHINX: # %bb.0: # %start
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI34_0)
-; RV32IZHINX-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZHINX-NEXT: fmax.s a0, a0, zero
+; RV32IZHINX-NEXT: lui a1, 292864
+; RV32IZHINX-NEXT: addi a1, a1, -256
; RV32IZHINX-NEXT: fmin.s a0, a0, a1
; RV32IZHINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_wu_s_sat_i16:
; RV64IZHINX: # %bb.0: # %start
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI34_0)
-; RV64IZHINX-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: fmax.s a0, a0, zero
+; RV64IZHINX-NEXT: lui a1, 292864
+; RV64IZHINX-NEXT: addiw a1, a1, -256
; RV64IZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZDINXZHINX: # %bb.0: # %start
-; RV32IZDINXZHINX-NEXT: lui a1, %hi(.LCPI34_0)
-; RV32IZDINXZHINX-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINX-NEXT: fmax.s a0, a0, zero
+; RV32IZDINXZHINX-NEXT: lui a1, 292864
+; RV32IZDINXZHINX-NEXT: addi a1, a1, -256
; RV32IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV32IZDINXZHINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_wu_s_sat_i16:
; RV64IZDINXZHINX: # %bb.0: # %start
-; RV64IZDINXZHINX-NEXT: lui a1, %hi(.LCPI34_0)
-; RV64IZDINXZHINX-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, zero
+; RV64IZDINXZHINX-NEXT: lui a1, 292864
+; RV64IZDINXZHINX-NEXT: addiw a1, a1, -256
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZDINXZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
@@ -7082,40 +7082,40 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
; CHECK32-IZHINXMIN: # %bb.0: # %start
-; CHECK32-IZHINXMIN-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECK32-IZHINXMIN-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK32-IZHINXMIN-NEXT: lui a1, 292864
+; CHECK32-IZHINXMIN-NEXT: addi a1, a1, -256
; CHECK32-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
; CHECK64-IZHINXMIN: # %bb.0: # %start
-; CHECK64-IZHINXMIN-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECK64-IZHINXMIN-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK64-IZHINXMIN-NEXT: lui a1, 292864
+; CHECK64-IZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %start
-; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, 292864
+; CHECK32-IZDINXZHINXMIN-NEXT: addi a1, a1, -256
; CHECK32-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
-; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECK64-IZDINXZHINXMIN-NEXT: lw a1, %lo(.LCPI34_0)(a1)
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
+; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 292864
+; CHECK64-IZDINXZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index 4c39885176f01a..2ebc28c2ebd440 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -70,15 +70,15 @@ define half @half_imm_op(half %a) nounwind {
;
; RV32IZHINX-LABEL: half_imm_op:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT: li a1, 15
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fadd.h a0, a0, a1
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: half_imm_op:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT: li a1, 15
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fadd.h a0, a0, a1
; RV64IZHINX-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index 40363b321848d7..3e0f838270aa5d 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -2132,8 +2132,8 @@ define half @floor_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: floor_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI17_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB17_2
@@ -2223,8 +2223,8 @@ define half @ceil_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: ceil_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI18_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
@@ -2314,8 +2314,8 @@ define half @trunc_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: trunc_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI19_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB19_2
@@ -2405,8 +2405,8 @@ define half @rint_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: rint_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI20_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
@@ -2616,8 +2616,8 @@ define half @round_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: round_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI22_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
@@ -2707,8 +2707,8 @@ define half @roundeven_f16(half %a) nounwind {
;
; CHECKIZHINX-LABEL: roundeven_f16:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI23_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB23_2
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
index 04a8a66f44598f..0b93c8789fca5e 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
@@ -28,8 +28,8 @@ define signext i32 @test_floor_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_floor_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI0_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB0_2
@@ -153,8 +153,8 @@ define i64 @test_floor_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_floor_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB1_2
@@ -174,9 +174,9 @@ define i64 @test_floor_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -203,8 +203,8 @@ define i64 @test_floor_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_floor_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB1_2
@@ -317,9 +317,9 @@ define i64 @test_floor_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -381,8 +381,8 @@ define signext i32 @test_floor_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_floor_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI2_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB2_2
@@ -400,8 +400,8 @@ define signext i32 @test_floor_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_floor_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI2_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB2_2
@@ -555,8 +555,8 @@ define i64 @test_floor_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_floor_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB3_2
@@ -574,9 +574,9 @@ define i64 @test_floor_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI3_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI3_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -590,8 +590,8 @@ define i64 @test_floor_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_floor_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB3_2
@@ -689,9 +689,9 @@ define i64 @test_floor_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI3_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI3_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -740,8 +740,8 @@ define signext i32 @test_ceil_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_ceil_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI4_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB4_2
@@ -865,8 +865,8 @@ define i64 @test_ceil_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_ceil_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB5_2
@@ -886,9 +886,9 @@ define i64 @test_ceil_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -915,8 +915,8 @@ define i64 @test_ceil_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_ceil_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB5_2
@@ -1029,9 +1029,9 @@ define i64 @test_ceil_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -1093,8 +1093,8 @@ define signext i32 @test_ceil_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI6_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB6_2
@@ -1112,8 +1112,8 @@ define signext i32 @test_ceil_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI6_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB6_2
@@ -1267,8 +1267,8 @@ define i64 @test_ceil_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_ceil_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB7_2
@@ -1286,9 +1286,9 @@ define i64 @test_ceil_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI7_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI7_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -1302,8 +1302,8 @@ define i64 @test_ceil_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_ceil_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB7_2
@@ -1401,9 +1401,9 @@ define i64 @test_ceil_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI7_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI7_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -1452,8 +1452,8 @@ define signext i32 @test_trunc_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_trunc_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI8_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB8_2
@@ -1577,8 +1577,8 @@ define i64 @test_trunc_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_trunc_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB9_2
@@ -1598,9 +1598,9 @@ define i64 @test_trunc_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -1627,8 +1627,8 @@ define i64 @test_trunc_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_trunc_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB9_2
@@ -1741,9 +1741,9 @@ define i64 @test_trunc_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -1805,8 +1805,8 @@ define signext i32 @test_trunc_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI10_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB10_2
@@ -1824,8 +1824,8 @@ define signext i32 @test_trunc_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI10_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB10_2
@@ -1979,8 +1979,8 @@ define i64 @test_trunc_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_trunc_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB11_2
@@ -1998,9 +1998,9 @@ define i64 @test_trunc_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI11_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI11_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -2014,8 +2014,8 @@ define i64 @test_trunc_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_trunc_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB11_2
@@ -2113,9 +2113,9 @@ define i64 @test_trunc_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI11_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI11_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -2164,8 +2164,8 @@ define signext i32 @test_round_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_round_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI12_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB12_2
@@ -2289,8 +2289,8 @@ define i64 @test_round_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_round_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB13_2
@@ -2310,9 +2310,9 @@ define i64 @test_round_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -2339,8 +2339,8 @@ define i64 @test_round_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_round_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB13_2
@@ -2453,9 +2453,9 @@ define i64 @test_round_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -2517,8 +2517,8 @@ define signext i32 @test_round_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_round_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI14_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB14_2
@@ -2536,8 +2536,8 @@ define signext i32 @test_round_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_round_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI14_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB14_2
@@ -2691,8 +2691,8 @@ define i64 @test_round_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_round_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB15_2
@@ -2710,9 +2710,9 @@ define i64 @test_round_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI15_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI15_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -2726,8 +2726,8 @@ define i64 @test_round_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_round_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB15_2
@@ -2825,9 +2825,9 @@ define i64 @test_round_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI15_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI15_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -2876,8 +2876,8 @@ define signext i32 @test_roundeven_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_roundeven_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI16_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB16_2
@@ -3001,8 +3001,8 @@ define i64 @test_roundeven_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_roundeven_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB17_2
@@ -3022,9 +3022,9 @@ define i64 @test_roundeven_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -3051,8 +3051,8 @@ define i64 @test_roundeven_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_roundeven_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB17_2
@@ -3165,9 +3165,9 @@ define i64 @test_roundeven_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -3229,8 +3229,8 @@ define signext i32 @test_roundeven_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI18_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB18_2
@@ -3248,8 +3248,8 @@ define signext i32 @test_roundeven_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI18_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB18_2
@@ -3403,8 +3403,8 @@ define i64 @test_roundeven_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_roundeven_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB19_2
@@ -3422,9 +3422,9 @@ define i64 @test_roundeven_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI19_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI19_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -3438,8 +3438,8 @@ define i64 @test_roundeven_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_roundeven_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB19_2
@@ -3537,9 +3537,9 @@ define i64 @test_roundeven_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI19_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI19_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -3588,8 +3588,8 @@ define signext i32 @test_rint_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_rint_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI20_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
@@ -3713,8 +3713,8 @@ define i64 @test_rint_si64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_rint_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB21_2
@@ -3734,9 +3734,9 @@ define i64 @test_rint_si64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s2, s1
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixsfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2)
; RV32IZHINX-NEXT: and a0, s2, a0
+; RV32IZHINX-NEXT: lui a2, 389120
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a4, a2, s0
; RV32IZHINX-NEXT: neg a2, a4
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -3763,8 +3763,8 @@ define i64 @test_rint_si64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_rint_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB21_2
@@ -3877,9 +3877,9 @@ define i64 @test_rint_si64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s2, s1
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixsfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s2, a0
+; RV32IZHINXMIN-NEXT: lui a2, 389120
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a4
; RV32IZHINXMIN-NEXT: or a0, a2, a0
@@ -3941,8 +3941,8 @@ define signext i32 @test_rint_ui32(half %x) {
;
; RV32IZHINX-LABEL: test_rint_ui32:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI22_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB22_2
@@ -3960,8 +3960,8 @@ define signext i32 @test_rint_ui32(half %x) {
;
; RV64IZHINX-LABEL: test_rint_ui32:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI22_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB22_2
@@ -4115,8 +4115,8 @@ define i64 @test_rint_ui64(half %x) nounwind {
;
; RV32IZHINX-LABEL: test_rint_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB23_2
@@ -4134,9 +4134,9 @@ define i64 @test_rint_ui64(half %x) nounwind {
; RV32IZHINX-NEXT: neg s1, a0
; RV32IZHINX-NEXT: mv a0, s0
; RV32IZHINX-NEXT: call __fixunssfdi
-; RV32IZHINX-NEXT: lui a2, %hi(.LCPI23_1)
-; RV32IZHINX-NEXT: lw a2, %lo(.LCPI23_1)(a2)
; RV32IZHINX-NEXT: and a0, s1, a0
+; RV32IZHINX-NEXT: lui a2, 391168
+; RV32IZHINX-NEXT: addi a2, a2, -1
; RV32IZHINX-NEXT: flt.s a2, a2, s0
; RV32IZHINX-NEXT: neg a2, a2
; RV32IZHINX-NEXT: or a0, a2, a0
@@ -4150,8 +4150,8 @@ define i64 @test_rint_ui64(half %x) nounwind {
;
; RV64IZHINX-LABEL: test_rint_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB23_2
@@ -4249,9 +4249,9 @@ define i64 @test_rint_ui64(half %x) nounwind {
; RV32IZHINXMIN-NEXT: neg s1, a0
; RV32IZHINXMIN-NEXT: mv a0, s0
; RV32IZHINXMIN-NEXT: call __fixunssfdi
-; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI23_0)(a2)
; RV32IZHINXMIN-NEXT: and a0, s1, a0
+; RV32IZHINXMIN-NEXT: lui a2, 391168
+; RV32IZHINXMIN-NEXT: addi a2, a2, -1
; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
; RV32IZHINXMIN-NEXT: neg a2, a2
; RV32IZHINXMIN-NEXT: or a0, a2, a0
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 2a1e0cfdda83e3..8eeea074265753 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -29,8 +29,8 @@ define signext i8 @test_floor_si8(half %x) {
;
; RV32IZHINX-LABEL: test_floor_si8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI0_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB0_2
@@ -44,8 +44,8 @@ define signext i8 @test_floor_si8(half %x) {
;
; RV64IZHINX-LABEL: test_floor_si8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI0_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB0_2
@@ -144,8 +144,8 @@ define signext i16 @test_floor_si16(half %x) {
;
; RV32IZHINX-LABEL: test_floor_si16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB1_2
@@ -159,8 +159,8 @@ define signext i16 @test_floor_si16(half %x) {
;
; RV64IZHINX-LABEL: test_floor_si16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB1_2
@@ -254,8 +254,8 @@ define signext i32 @test_floor_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_floor_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI2_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB2_2
@@ -335,8 +335,8 @@ define i64 @test_floor_si64(half %x) {
;
; RV32IZHINX-LABEL: test_floor_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB3_2
@@ -356,8 +356,8 @@ define i64 @test_floor_si64(half %x) {
;
; RV64IZHINX-LABEL: test_floor_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB3_2
@@ -466,8 +466,8 @@ define zeroext i8 @test_floor_ui8(half %x) {
;
; RV32IZHINX-LABEL: test_floor_ui8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI4_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB4_2
@@ -481,8 +481,8 @@ define zeroext i8 @test_floor_ui8(half %x) {
;
; RV64IZHINX-LABEL: test_floor_ui8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI4_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB4_2
@@ -581,8 +581,8 @@ define zeroext i16 @test_floor_ui16(half %x) {
;
; RV32IZHINX-LABEL: test_floor_ui16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB5_2
@@ -596,8 +596,8 @@ define zeroext i16 @test_floor_ui16(half %x) {
;
; RV64IZHINX-LABEL: test_floor_ui16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB5_2
@@ -691,8 +691,8 @@ define signext i32 @test_floor_ui32(half %x) {
;
; CHECKIZHINX-LABEL: test_floor_ui32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI6_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB6_2
@@ -772,8 +772,8 @@ define i64 @test_floor_ui64(half %x) {
;
; RV32IZHINX-LABEL: test_floor_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB7_2
@@ -793,8 +793,8 @@ define i64 @test_floor_ui64(half %x) {
;
; RV64IZHINX-LABEL: test_floor_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB7_2
@@ -903,8 +903,8 @@ define signext i8 @test_ceil_si8(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_si8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI8_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB8_2
@@ -918,8 +918,8 @@ define signext i8 @test_ceil_si8(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_si8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI8_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB8_2
@@ -1018,8 +1018,8 @@ define signext i16 @test_ceil_si16(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_si16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB9_2
@@ -1033,8 +1033,8 @@ define signext i16 @test_ceil_si16(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_si16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB9_2
@@ -1128,8 +1128,8 @@ define signext i32 @test_ceil_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_ceil_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI10_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB10_2
@@ -1209,8 +1209,8 @@ define i64 @test_ceil_si64(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB11_2
@@ -1230,8 +1230,8 @@ define i64 @test_ceil_si64(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB11_2
@@ -1340,8 +1340,8 @@ define zeroext i8 @test_ceil_ui8(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_ui8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB12_2
@@ -1355,8 +1355,8 @@ define zeroext i8 @test_ceil_ui8(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_ui8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI12_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB12_2
@@ -1455,8 +1455,8 @@ define zeroext i16 @test_ceil_ui16(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_ui16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB13_2
@@ -1470,8 +1470,8 @@ define zeroext i16 @test_ceil_ui16(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_ui16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB13_2
@@ -1565,8 +1565,8 @@ define signext i32 @test_ceil_ui32(half %x) {
;
; CHECKIZHINX-LABEL: test_ceil_ui32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI14_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB14_2
@@ -1646,8 +1646,8 @@ define i64 @test_ceil_ui64(half %x) {
;
; RV32IZHINX-LABEL: test_ceil_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB15_2
@@ -1667,8 +1667,8 @@ define i64 @test_ceil_ui64(half %x) {
;
; RV64IZHINX-LABEL: test_ceil_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB15_2
@@ -1777,8 +1777,8 @@ define signext i8 @test_trunc_si8(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_si8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI16_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB16_2
@@ -1792,8 +1792,8 @@ define signext i8 @test_trunc_si8(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_si8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI16_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB16_2
@@ -1892,8 +1892,8 @@ define signext i16 @test_trunc_si16(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_si16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB17_2
@@ -1907,8 +1907,8 @@ define signext i16 @test_trunc_si16(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_si16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB17_2
@@ -2002,8 +2002,8 @@ define signext i32 @test_trunc_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_trunc_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI18_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
@@ -2083,8 +2083,8 @@ define i64 @test_trunc_si64(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB19_2
@@ -2104,8 +2104,8 @@ define i64 @test_trunc_si64(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB19_2
@@ -2214,8 +2214,8 @@ define zeroext i8 @test_trunc_ui8(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_ui8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI20_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB20_2
@@ -2229,8 +2229,8 @@ define zeroext i8 @test_trunc_ui8(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_ui8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI20_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB20_2
@@ -2329,8 +2329,8 @@ define zeroext i16 @test_trunc_ui16(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_ui16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB21_2
@@ -2344,8 +2344,8 @@ define zeroext i16 @test_trunc_ui16(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_ui16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB21_2
@@ -2439,8 +2439,8 @@ define signext i32 @test_trunc_ui32(half %x) {
;
; CHECKIZHINX-LABEL: test_trunc_ui32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI22_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
@@ -2520,8 +2520,8 @@ define i64 @test_trunc_ui64(half %x) {
;
; RV32IZHINX-LABEL: test_trunc_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB23_2
@@ -2541,8 +2541,8 @@ define i64 @test_trunc_ui64(half %x) {
;
; RV64IZHINX-LABEL: test_trunc_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB23_2
@@ -2651,8 +2651,8 @@ define signext i8 @test_round_si8(half %x) {
;
; RV32IZHINX-LABEL: test_round_si8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI24_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI24_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB24_2
@@ -2666,8 +2666,8 @@ define signext i8 @test_round_si8(half %x) {
;
; RV64IZHINX-LABEL: test_round_si8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI24_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI24_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB24_2
@@ -2766,8 +2766,8 @@ define signext i16 @test_round_si16(half %x) {
;
; RV32IZHINX-LABEL: test_round_si16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI25_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI25_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB25_2
@@ -2781,8 +2781,8 @@ define signext i16 @test_round_si16(half %x) {
;
; RV64IZHINX-LABEL: test_round_si16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI25_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI25_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB25_2
@@ -2876,8 +2876,8 @@ define signext i32 @test_round_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_round_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI26_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI26_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB26_2
@@ -2957,8 +2957,8 @@ define i64 @test_round_si64(half %x) {
;
; RV32IZHINX-LABEL: test_round_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI27_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI27_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB27_2
@@ -2978,8 +2978,8 @@ define i64 @test_round_si64(half %x) {
;
; RV64IZHINX-LABEL: test_round_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI27_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI27_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB27_2
@@ -3088,8 +3088,8 @@ define zeroext i8 @test_round_ui8(half %x) {
;
; RV32IZHINX-LABEL: test_round_ui8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI28_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI28_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB28_2
@@ -3103,8 +3103,8 @@ define zeroext i8 @test_round_ui8(half %x) {
;
; RV64IZHINX-LABEL: test_round_ui8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI28_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI28_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB28_2
@@ -3203,8 +3203,8 @@ define zeroext i16 @test_round_ui16(half %x) {
;
; RV32IZHINX-LABEL: test_round_ui16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI29_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI29_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB29_2
@@ -3218,8 +3218,8 @@ define zeroext i16 @test_round_ui16(half %x) {
;
; RV64IZHINX-LABEL: test_round_ui16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI29_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI29_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB29_2
@@ -3313,8 +3313,8 @@ define signext i32 @test_round_ui32(half %x) {
;
; CHECKIZHINX-LABEL: test_round_ui32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI30_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI30_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB30_2
@@ -3394,8 +3394,8 @@ define i64 @test_round_ui64(half %x) {
;
; RV32IZHINX-LABEL: test_round_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI31_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI31_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB31_2
@@ -3415,8 +3415,8 @@ define i64 @test_round_ui64(half %x) {
;
; RV64IZHINX-LABEL: test_round_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI31_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI31_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB31_2
@@ -3525,8 +3525,8 @@ define signext i8 @test_roundeven_si8(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_si8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI32_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI32_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB32_2
@@ -3540,8 +3540,8 @@ define signext i8 @test_roundeven_si8(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_si8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI32_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI32_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB32_2
@@ -3640,8 +3640,8 @@ define signext i16 @test_roundeven_si16(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_si16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI33_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI33_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB33_2
@@ -3655,8 +3655,8 @@ define signext i16 @test_roundeven_si16(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_si16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI33_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI33_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB33_2
@@ -3750,8 +3750,8 @@ define signext i32 @test_roundeven_si32(half %x) {
;
; CHECKIZHINX-LABEL: test_roundeven_si32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI34_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB34_2
@@ -3831,8 +3831,8 @@ define i64 @test_roundeven_si64(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_si64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI35_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI35_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB35_2
@@ -3852,8 +3852,8 @@ define i64 @test_roundeven_si64(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_si64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI35_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI35_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB35_2
@@ -3962,8 +3962,8 @@ define zeroext i8 @test_roundeven_ui8(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_ui8:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI36_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI36_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB36_2
@@ -3977,8 +3977,8 @@ define zeroext i8 @test_roundeven_ui8(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_ui8:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI36_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI36_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB36_2
@@ -4077,8 +4077,8 @@ define zeroext i16 @test_roundeven_ui16(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_ui16:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI37_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI37_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB37_2
@@ -4092,8 +4092,8 @@ define zeroext i16 @test_roundeven_ui16(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_ui16:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI37_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI37_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB37_2
@@ -4187,8 +4187,8 @@ define signext i32 @test_roundeven_ui32(half %x) {
;
; CHECKIZHINX-LABEL: test_roundeven_ui32:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI38_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI38_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB38_2
@@ -4268,8 +4268,8 @@ define i64 @test_roundeven_ui64(half %x) {
;
; RV32IZHINX-LABEL: test_roundeven_ui64:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a1, %hi(.LCPI39_0)
-; RV32IZHINX-NEXT: lh a1, %lo(.LCPI39_0)(a1)
+; RV32IZHINX-NEXT: li a1, 25
+; RV32IZHINX-NEXT: slli a1, a1, 10
; RV32IZHINX-NEXT: fabs.h a2, a0
; RV32IZHINX-NEXT: flt.h a1, a2, a1
; RV32IZHINX-NEXT: beqz a1, .LBB39_2
@@ -4289,8 +4289,8 @@ define i64 @test_roundeven_ui64(half %x) {
;
; RV64IZHINX-LABEL: test_roundeven_ui64:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a1, %hi(.LCPI39_0)
-; RV64IZHINX-NEXT: lh a1, %lo(.LCPI39_0)(a1)
+; RV64IZHINX-NEXT: li a1, 25
+; RV64IZHINX-NEXT: slli a1, a1, 10
; RV64IZHINX-NEXT: fabs.h a2, a0
; RV64IZHINX-NEXT: flt.h a1, a2, a1
; RV64IZHINX-NEXT: beqz a1, .LBB39_2
@@ -4424,8 +4424,8 @@ define half @test_floor_half(half %x) {
;
; CHECKIZHINX-LABEL: test_floor_half:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI40_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI40_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB40_2
@@ -4508,8 +4508,8 @@ define half @test_ceil_half(half %x) {
;
; CHECKIZHINX-LABEL: test_ceil_half:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI41_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI41_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB41_2
@@ -4592,8 +4592,8 @@ define half @test_trunc_half(half %x) {
;
; CHECKIZHINX-LABEL: test_trunc_half:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI42_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI42_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB42_2
@@ -4676,8 +4676,8 @@ define half @test_round_half(half %x) {
;
; CHECKIZHINX-LABEL: test_round_half:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI43_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI43_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB43_2
@@ -4760,8 +4760,8 @@ define half @test_roundeven_half(half %x) {
;
; CHECKIZHINX-LABEL: test_roundeven_half:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI44_0)
-; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI44_0)(a1)
+; CHECKIZHINX-NEXT: li a1, 25
+; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
; CHECKIZHINX-NEXT: beqz a1, .LBB44_2
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