[llvm] [RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (PR #107297)

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git-clang-format --diff f574b9c9297538a8d471658564619be3ad6e87dd e19eaa210cc8b0420d898b7aef02a105314f7ed3 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 714129262b..dbdef7a773 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1099,7 +1099,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     }
 
     // TODO: Could we merge some code with zvfhmin?
-    if (Subtarget.hasVInstructionsBF16Minimal()) { for (MVT VT : BF16VecVTs) {
+    if (Subtarget.hasVInstructionsBF16Minimal()) {
+      for (MVT VT : BF16VecVTs) {
         if (!isTypeLegal(VT))
           continue;
         setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);

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https://github.com/llvm/llvm-project/pull/107297