[llvm] [RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (PR #107297)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 12:42:33 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
This allows odd sized vector load/store to be legalized to a VP_LOAD/STORE using EVL.
I changed the bf16 tests in fixed-vectors-load.ll and fixed-vectors-store.ll to use an illegal type to be consistent with the intent of these files. A legal type is already tested in fixed-vectors-load-store.ll
---
Patch is 158.17 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/107297.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll (+963-1823)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll (+4-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bc661c72e5ecca..714129262b9def 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1099,8 +1099,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
// TODO: Could we merge some code with zvfhmin?
- if (Subtarget.hasVInstructionsBF16Minimal()) {
- for (MVT VT : BF16VecVTs) {
+ if (Subtarget.hasVInstructionsBF16Minimal()) { for (MVT VT : BF16VecVTs) {
if (!isTypeLegal(VT))
continue;
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
@@ -1317,6 +1316,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// FIXME: mload, mstore, mgather, mscatter, vp_load/store,
// vp_stride_load/store, vp_gather/scatter can be hoisted to here.
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
+ setOperationAction({ISD::VP_LOAD, ISD::VP_STORE}, VT, Custom);
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
@@ -1378,8 +1378,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(
{ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom);
- setOperationAction({ISD::VP_LOAD, ISD::VP_STORE,
- ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
+ setOperationAction({ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
ISD::EXPERIMENTAL_VP_STRIDED_STORE, ISD::VP_GATHER,
ISD::VP_SCATTER},
VT, Custom);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index 56cd718536daa4..d996a9c05aca4d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -49,42 +49,20 @@ define void @fadd_v6f16(ptr %x, ptr %y) {
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
-; ZVFHMIN-RV32-LABEL: fadd_v6f16:
-; ZVFHMIN-RV32: # %bb.0:
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV32-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV32-NEXT: addi a1, a0, 8
-; ZVFHMIN-RV32-NEXT: vse32.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVFHMIN-RV32-NEXT: vse16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: ret
-;
-; ZVFHMIN-RV64-LABEL: fadd_v6f16:
-; ZVFHMIN-RV64: # %bb.0:
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV64-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV64-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vse64.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV64-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV64-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: ret
+; ZVFHMIN-LABEL: fadd_v6f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfadd.vv v8, v8, v10
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vse16.v v9, (a0)
+; ZVFHMIN-NEXT: ret
%a = load <6 x half>, ptr %x
%b = load <6 x half>, ptr %y
%c = fadd <6 x half> %a, %b
@@ -173,42 +151,20 @@ define void @fsub_v6f16(ptr %x, ptr %y) {
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
-; ZVFHMIN-RV32-LABEL: fsub_v6f16:
-; ZVFHMIN-RV32: # %bb.0:
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV32-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV32-NEXT: addi a1, a0, 8
-; ZVFHMIN-RV32-NEXT: vse32.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVFHMIN-RV32-NEXT: vse16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: ret
-;
-; ZVFHMIN-RV64-LABEL: fsub_v6f16:
-; ZVFHMIN-RV64: # %bb.0:
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV64-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV64-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vse64.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV64-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV64-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: ret
+; ZVFHMIN-LABEL: fsub_v6f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfsub.vv v8, v8, v10
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vse16.v v9, (a0)
+; ZVFHMIN-NEXT: ret
%a = load <6 x half>, ptr %x
%b = load <6 x half>, ptr %y
%c = fsub <6 x half> %a, %b
@@ -297,42 +253,20 @@ define void @fmul_v6f16(ptr %x, ptr %y) {
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
-; ZVFHMIN-RV32-LABEL: fmul_v6f16:
-; ZVFHMIN-RV32: # %bb.0:
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV32-NEXT: vfmul.vv v8, v8, v10
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV32-NEXT: addi a1, a0, 8
-; ZVFHMIN-RV32-NEXT: vse32.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVFHMIN-RV32-NEXT: vse16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: ret
-;
-; ZVFHMIN-RV64-LABEL: fmul_v6f16:
-; ZVFHMIN-RV64: # %bb.0:
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV64-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV64-NEXT: vfmul.vv v8, v8, v10
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vse64.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV64-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV64-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: ret
+; ZVFHMIN-LABEL: fmul_v6f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmul.vv v8, v8, v10
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vse16.v v9, (a0)
+; ZVFHMIN-NEXT: ret
%a = load <6 x half>, ptr %x
%b = load <6 x half>, ptr %y
%c = fmul <6 x half> %a, %b
@@ -421,42 +355,20 @@ define void @fdiv_v6f16(ptr %x, ptr %y) {
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
-; ZVFHMIN-RV32-LABEL: fdiv_v6f16:
-; ZVFHMIN-RV32: # %bb.0:
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV32-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV32-NEXT: vfdiv.vv v8, v8, v10
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV32-NEXT: addi a1, a0, 8
-; ZVFHMIN-RV32-NEXT: vse32.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVFHMIN-RV32-NEXT: vse16.v v9, (a0)
-; ZVFHMIN-RV32-NEXT: ret
-;
-; ZVFHMIN-RV64-LABEL: fdiv_v6f16:
-; ZVFHMIN-RV64: # %bb.0:
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN-RV64-NEXT: vle16.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-RV64-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-RV64-NEXT: vfdiv.vv v8, v8, v10
-; ZVFHMIN-RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vfncvt.f.f.w v9, v8
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vse64.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV64-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV64-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: ret
+; ZVFHMIN-LABEL: fdiv_v6f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfdiv.vv v8, v8, v10
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vse16.v v9, (a0)
+; ZVFHMIN-NEXT: ret
%a = load <6 x half>, ptr %x
%b = load <6 x half>, ptr %y
%c = fdiv <6 x half> %a, %b
@@ -576,115 +488,55 @@ define void @fneg_v6f16(ptr %x) {
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
-; ZVFHMIN-RV32-LABEL: fneg_v6f16:
-; ZVFHMIN-RV32: # %bb.0:
-; ZVFHMIN-RV32-NEXT: addi sp, sp, -16
-; ZVFHMIN-RV32-NEXT: .cfi_def_cfa_offset 16
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
-; ZVFHMIN-RV32-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-RV32-NEXT: mv a1, sp
-; ZVFHMIN-RV32-NEXT: vse16.v v8, (a1)
-; ZVFHMIN-RV32-NEXT: flh fa5, 2(sp)
-; ZVFHMIN-RV32-NEXT: flh fa4, 0(sp)
-; ZVFHMIN-RV32-NEXT: flh fa3, 4(sp)
-; ZVFHMIN-RV32-NEXT: fmv.x.h a1, fa5
-; ZVFHMIN-RV32-NEXT: fmv.x.h a2, fa4
-; ZVFHMIN-RV32-NEXT: lui a3, 1048568
-; ZVFHMIN-RV32-NEXT: fmv.x.h a4, fa3
-; ZVFHMIN-RV32-NEXT: flh fa5, 6(sp)
-; ZVFHMIN-RV32-NEXT: xor a1, a1, a3
-; ZVFHMIN-RV32-NEXT: xor a2, a2, a3
-; ZVFHMIN-RV32-NEXT: vmv.v.x v8, a2
-; ZVFHMIN-RV32-NEXT: fmv.x.h a5, fa5
-; ZVFHMIN-RV32-NEXT: flh fa5, 10(sp)
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a1
-; ZVFHMIN-RV32-NEXT: xor a4, a4, a3
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a4
-; ZVFHMIN-RV32-NEXT: fmv.x.h a6, fa5
-; ZVFHMIN-RV32-NEXT: flh fa5, 8(sp)
-; ZVFHMIN-RV32-NEXT: xor a5, a5, a3
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a5
-; ZVFHMIN-RV32-NEXT: xor a6, a6, a3
-; ZVFHMIN-RV32-NEXT: fmv.x.h a7, fa5
-; ZVFHMIN-RV32-NEXT: flh fa5, 12(sp)
-; ZVFHMIN-RV32-NEXT: lui t0, 8
-; ZVFHMIN-RV32-NEXT: xor a7, a7, t0
-; ZVFHMIN-RV32-NEXT: vmv.v.x v9, a7
-; ZVFHMIN-RV32-NEXT: fmv.x.h a7, fa5
-; ZVFHMIN-RV32-NEXT: flh fa5, 14(sp)
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v9, v9, a6
-; ZVFHMIN-RV32-NEXT: xor a6, a7, a3
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v9, v9, a6
-; ZVFHMIN-RV32-NEXT: fmv.x.h a6, fa5
-; ZVFHMIN-RV32-NEXT: xor a3, a6, a3
-; ZVFHMIN-RV32-NEXT: vmv.v.i v0, 15
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v9, v9, a3
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v9, v8, 4, v0.t
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVFHMIN-RV32-NEXT: vmv.v.x v8, a2
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a1
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a4
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a5
-; ZVFHMIN-RV32-NEXT: vse16.v v8, (a0)
-; ZVFHMIN-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV32-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV32-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV32-NEXT: addi sp, sp, 16
-; ZVFHMIN-RV32-NEXT: ret
-;
-; ZVFHMIN-RV64-LABEL: fneg_v6f16:
-; ZVFHMIN-RV64: # %bb.0:
-; ZVFHMIN-RV64-NEXT: addi sp, sp, -16
-; ZVFHMIN-RV64-NEXT: .cfi_def_cfa_offset 16
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
-; ZVFHMIN-RV64-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: mv a1, sp
-; ZVFHMIN-RV64-NEXT: vse16.v v8, (a1)
-; ZVFHMIN-RV64-NEXT: flh fa5, 2(sp)
-; ZVFHMIN-RV64-NEXT: flh fa4, 0(sp)
-; ZVFHMIN-RV64-NEXT: flh fa3, 4(sp)
-; ZVFHMIN-RV64-NEXT: fmv.x.h a1, fa5
-; ZVFHMIN-RV64-NEXT: fmv.x.h a2, fa4
-; ZVFHMIN-RV64-NEXT: lui a3, 1048568
-; ZVFHMIN-RV64-NEXT: fmv.x.h a4, fa3
-; ZVFHMIN-RV64-NEXT: flh fa5, 6(sp)
-; ZVFHMIN-RV64-NEXT: lui a5, 8
-; ZVFHMIN-RV64-NEXT: xor a2, a2, a5
-; ZVFHMIN-RV64-NEXT: vmv.v.x v8, a2
-; ZVFHMIN-RV64-NEXT: fmv.x.h a2, fa5
-; ZVFHMIN-RV64-NEXT: flh fa5, 10(sp)
-; ZVFHMIN-RV64-NEXT: xor a1, a1, a3
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v8, v8, a1
-; ZVFHMIN-RV64-NEXT: xor a4, a4, a3
-; ZVFHMIN-RV64-NEXT: fmv.x.h a1, fa5
-; ZVFHMIN-RV64-NEXT: flh fa5, 8(sp)
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v8, v8, a4
-; ZVFHMIN-RV64-NEXT: xor a2, a2, a3
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v8, v8, a2
-; ZVFHMIN-RV64-NEXT: fmv.x.h a2, fa5
-; ZVFHMIN-RV64-NEXT: flh fa5, 12(sp)
-; ZVFHMIN-RV64-NEXT: xor a1, a1, a3
-; ZVFHMIN-RV64-NEXT: xor a2, a2, a5
-; ZVFHMIN-RV64-NEXT: vmv.v.x v9, a2
-; ZVFHMIN-RV64-NEXT: fmv.x.h a2, fa5
-; ZVFHMIN-RV64-NEXT: flh fa5, 14(sp)
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v9, v9, a1
-; ZVFHMIN-RV64-NEXT: xor a2, a2, a3
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v9, v9, a2
-; ZVFHMIN-RV64-NEXT: fmv.x.h a1, fa5
-; ZVFHMIN-RV64-NEXT: xor a1, a1, a3
-; ZVFHMIN-RV64-NEXT: vmv.v.i v0, 15
-; ZVFHMIN-RV64-NEXT: vslide1down.vx v9, v9, a1
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v9, v8, 4, v0.t
-; ZVFHMIN-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-RV64-NEXT: vse64.v v9, (a0)
-; ZVFHMIN-RV64-NEXT: vslidedown.vi v8, v9, 2
-; ZVFHMIN-RV64-NEXT: addi a0, a0, 8
-; ZVFHMIN-RV64-NEXT: vse32.v v8, (a0)
-; ZVFHMIN-RV64-NEXT: addi sp, sp, 16
-; ZVFHMIN-RV64-NEXT: ret
+; ZVFHMIN-LABEL: fneg_v6f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: addi sp, sp, -16
+; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: mv a1, sp
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vse16.v v8, (a1)
+; ZVFHMIN-NEXT: flh fa5, 2(sp)
+; ZVFHMIN-NEXT: flh fa4, 0(sp)
+; ZVFHMIN-NEXT: flh fa3, 4(sp)
+; ZVFHMIN-NEXT: fmv.x.h a1, fa5
+; ZVFHMIN-NEXT: fmv.x.h a2, fa4
+; ZVFHMIN-NEXT: lui a3, 1048568
+; ZVFHMIN-NEXT: fmv.x.h a4, fa3
+; ZVFHMIN-NEXT: flh fa5, 6(sp)
+; ZVFHMIN-NEXT: lui a5, 8
+; ZVFHMIN-NEXT: xor a2, a2, a5
+; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: fmv.x.h a2, fa5
+; ZVFHMIN-NEXT: flh fa5, 10(sp)
+; ZVFHMIN-NEXT: xor a1, a1, a3
+; ZVFHMIN-NEXT: vslide1down.vx v8, v8, a1
+; ZVFHMIN-NEXT: xor a4, a4, a3
+; ZVFHMIN-NEXT: fmv.x.h a1, fa5
+; ZVFHMIN-NEXT: flh fa5, 8(sp)
+; ZVFHMIN-NEXT: vslide1down.vx v8, v8, a4
+; ZVFHMIN-NEXT: xor a2, a2, a3
+; ZVFHMIN-NEXT: vslide1down.vx v8, v8, a2
+; ZVFHMIN-NEXT: fmv.x.h a2, fa5
+; ZVFHMIN-NEXT: flh fa5, 12(sp)
+; ZVFHMIN-NEXT: xor a1, a1, a3
+; ZVFHMIN-NEXT: xor a2, a2, a5
+; ZVFHMIN-NEXT: vmv.v.x v9, a2
+; ZVFHMIN-NEXT: fmv.x.h a2, fa5
+; ZVFHMIN-NEXT: flh fa5, 14(sp)
+; ZVFHMIN-NEXT: vslide1down.vx v9, v9, a1
+; ZVFHMIN-NEXT: xor a2, a2, a3
+; ZVFHMIN-NEXT: vslide1down.vx v9, v9, a2
+; ZVFHMIN-NEXT: fmv.x.h a1, fa5
+; ZVFHMIN-NEXT: xor a1, a1, a3
+; ZVFHMIN-NEXT: vmv.v.i v0, 15
+; ZVFHMIN-NEXT: vslide1down.vx v9, v9, a1
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, mf2, ta, mu
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4, v0.t
+; ZVFHMIN-NEXT: vse16.v v9, (a0)
+; ZVFHMIN-NEXT: addi sp, sp, 16
+; ZVFHMIN-NEXT: ret
%a = load <6 x half>, ptr %x
%b = fneg <6 x half> %a
store <6 x half> %b, ptr %x
@@ -851,9 +703,10 @@ define void @fabs_v6f16(ptr %x) {
; ZVFHMIN-RV32: # %bb.0:
; ZVFHMIN-RV32-NEXT: addi sp, sp, -16
; ZVFHMIN-RV32-NEXT: .cfi_def_cfa_offset 16
-; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
+; ZVFHMIN-RV32-NEXT: vsetivli zero, 6, e16, mf2, ta, ma
; ZVFHMIN-RV32-NEXT: vle16.v v8, (a0)
; ZVFHMIN-RV32-NEXT: mv a1, sp
+; ZVFHMIN-RV32-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
; ZVFHMIN-RV32-NEXT: vse16.v v8, (a1)
; ZVFHMIN-RV32-NEXT: flh fa5, 2(sp)
; ZVFHMIN-RV32-NEXT: flh fa4, 0(sp)
@@ -864,44 +717,35 @@ define void @fabs_v6f16(ptr %x) {
; ZVFHMIN-RV32-NEXT: fmv.x.h a4, fa3
; ZVFHMIN-RV32-NEXT: flh fa5, 6(sp)
; ZVFHMIN-RV32-NEXT: addi a3, a3, -1
-; ZVFHMIN-RV32-NEXT: and a1, a1, a3
; ZVFHMIN-RV32-NEXT: and a2, a2, a3
-; ZVFHMIN-RV32-NEXT: fmv.x.h a5, fa5
-; ZVFHMIN-RV32-NEXT: flh fa5, 10(sp)
; ZVFHMIN-RV32-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-RV32-NEXT: fmv.x.h a2, fa5
+; ZVFHMIN-RV32-NEXT: flh fa5, 10(sp)
+; ZVFHMIN-RV32-NEXT: and a1, a1, a3
; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a1
; ZVFHMIN-RV32-NEXT: and a4, a4, a3
-; ZVFHMIN-RV32-NEXT: fmv.x.h a6, fa5
+; ZVFHMIN-RV32-NEXT: fmv.x.h a1, fa5
; ZVFHMIN-RV32-NEXT: flh fa5, 8(sp)
; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a4
-; ZVFHMIN-RV32-NEXT: and a5, a5, a3
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a5
-; ZVFHMIN-RV32-NEXT: fmv.x.h a7, fa5
+; ZVFHMIN-RV32-NEXT: and a2, a2, a3
+; ZVFHMIN-RV32-NEXT: vslide1down.vx v8, v8, a2
+; ZVFHMIN-RV32-NEXT: fmv.x.h a2, fa5
; ZVFHMIN-RV32-NEXT: flh fa5, 12(sp)
-; ZVFHMIN-RV32-NEXT: and a6, a6, a3
-; ZVFHMIN-RV32-NEXT: and a7, a7, a3
-; ZVFHMIN-RV32-NEXT: vmv.v.x v9, a7
-; ZVFHMIN-RV32-NEXT: fmv.x.h a7, fa5
+; ZVFHMIN-RV32-NEXT: and a1, a1, a3
+; ZVFHMIN-RV32-NEXT: and a2, a2, a3
+; ZVFHMIN-RV32-NEXT: vmv.v.x v9, a2
+; ZVFHMIN-RV32-NEXT: fmv.x.h a2, fa5
; ZVFHMIN-RV32-NEXT: flh fa5, 14(sp)
-; ZVFHMIN-RV32-NEXT: vslide1down.vx v9, v9, a6
-; ZVFHMIN-RV32-NEXT: and a6, a7, a3
-; ZVFHMIN-RV32...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/107297
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