[llvm] [RISCV] Select zero splats of EEW=64 on RV32 (PR #107205)

[Craig Topper via llvm-commits]

================
@@ -3452,10 +3452,37 @@ bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
   return true;
 }
 
+// Look for splats of zero. On RV32 a EEW=64 there may be a bitcast in between.
+//
+//   t72: nxv16i32 = RISCVISD::VMV_V_X_VL ...
+//   t73: v32i32 = extract_subvector t72, Constant:i32<0>
+//   t21: v16i64 = bitcast t73
+//   t42: nxv8i64 = insert_subvector undef:nxv8i64, t21, Constant:i32<0>
+static bool isZeroSplat(SDValue N) {
----------------
topperc wrote:

We make SPLAT_VECTOR of i64 legal on RV32 specifically so DAGCombine will turn BUILD_VECTOR into SPLAT_VECTOR.

```
        // Make SPLAT_VECTOR Legal so DAGCombine will convert splat vectors to   
        // it before type legalization for i64 vectors on RV32. It will then be  
        // type legalized to SPLAT_VECTOR_PARTS which we need to Custom handle.  
        // FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs      
        // improvements first.                                                   
        if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) {     
          setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);                      
          setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);               
        }  
```

In the affected tests, the type is larger than a legal type which I guess prevents the DAGCombine from triggering before type legalization. Then type legalization turns it into multiple i32 build_vectors. Maybe we should improve the combine or add a RISC-V combine?

https://github.com/llvm/llvm-project/pull/107205