[llvm] [RISCV] Correct the scheduler class for FCVT_S_BF16. (PR #107028)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

Use FCvtF16ToF32 instead of FCvtF32ToF16.

---
Full diff: https://github.com/llvm/llvm-project/pull/107028.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index bf6272317fda4d..52c4ee01bd44ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -31,7 +31,7 @@ let Predicates = [HasStdExtZfbfmin] in {
 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
                   Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
-                  Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+                  Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
 } // Predicates = [HasStdExtZfbfmin]
 
 //===----------------------------------------------------------------------===//

``````````

</details>


https://github.com/llvm/llvm-project/pull/107028