[llvm] [RISCV] Correct the scheduler class for FCVT_S_BF16. (PR #107028)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/107028

Use FCvtF16ToF32 instead of FCvtF32ToF16.

>From 45333544c2bd4a158c1eb1f69993badc99c224e7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Sep 2024 16:22:43 -0700
Subject: [PATCH] [RISCV] Correct the scheduler class for FCVT_S_BF16.

Use FCvtF16ToF32 instead of FCvtF32ToF16.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index bf6272317fda4d..52c4ee01bd44ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -31,7 +31,7 @@ let Predicates = [HasStdExtZfbfmin] in {
 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
                   Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
-                  Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+                  Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
 } // Predicates = [HasStdExtZfbfmin]
 
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