[llvm] [LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. (PR #104774)

[Paul Walker via llvm-commits]

================
@@ -29282,7 +29284,9 @@ void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {
     assert(VT.isVector() && Op0VT.isVector() && Op1VT.isVector() &&
            "Expected vectors!");
     // TODO: Enable assert once bogus creations have been fixed.
----------------
paulwalker-arm wrote:

As above.

https://github.com/llvm/llvm-project/pull/104774