[llvm] [LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. (PR #104774)

[Paul Walker via llvm-commits]

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@@ -29264,8 +29264,10 @@ void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {
     assert(OpVT.getSizeInBits() == VT.getSizeInBits() &&
            "Expected vectors of equal size!");
     // TODO: Enable assert once bogus creations have been fixed.
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paulwalker-arm wrote:

The assert is still disabled for scalable vectors.

https://github.com/llvm/llvm-project/pull/104774