[llvm] [LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. (PR #104774)

[Paul Walker via llvm-commits]

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@@ -19811,15 +19811,15 @@ static SDValue performConcatVectorsCombine(SDNode *N,
     // This optimization reduces instruction count.
     if (N00Opc == AArch64ISD::VLSHR && N10Opc == AArch64ISD::VLSHR &&
         N00->getOperand(1) == N10->getOperand(1)) {
-
       SDValue N000 = N00->getOperand(0);
       SDValue N100 = N10->getOperand(0);
       uint64_t N001ConstVal = N00->getConstantOperandVal(1),
                N101ConstVal = N10->getConstantOperandVal(1),
                NScalarSize = N->getValueType(0).getScalarSizeInBits();
 
       if (N001ConstVal == N101ConstVal && N001ConstVal > NScalarSize) {
-
+        N000 = DAG.getNode(AArch64ISD::NVCAST, dl, VT, N000);
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paulwalker-arm wrote:

By enabling the verification within verifyTargetSDNode for fixed-length vectors the code is tested (i.e. if you remove this code `make check` will assert.

https://github.com/llvm/llvm-project/pull/104774