[llvm] [AArch64] [CodeGen] [REV] Generate revC for all (srl (bswap x), C) instructions when C is 16 or 32 (PR #105375)

[via llvm-commits]

DTeachs wrote:

> GCC compiles the built-in function `__builtin_bswap16`, to the ARM instruction rev16, which reverses the byte order of 16-bit data. On the other Clang compiles the same built-in function to e.g.
> 
> ```
>         rev     w8, w0
>         lsr     w0, w8, #16
> ```
> 
> i.e. it performs a byte reversal of a 32-bit register, (which moves the lower half, which contains the 16-bit data, to the upper half) and then right shifts the reversed 16-bit data back to the lower half of the register. We can improve Clang codegen by generating `rev16` instead of `rev` and `lsr`, like GCC.

This is not correct. I mean, GCC does use rev16, but GCC also does an AND afterwards for truncation
<img width="1374" alt="Screenshot 2024-08-20 at 5 13 03 PM" src="https://github.com/user-attachments/assets/28566061-6459-471d-9b46-105df2ce6f9e">


https://github.com/llvm/llvm-project/pull/105375