[llvm] [AArch64] [CodeGen] [REV] Generate revC for all (srl (bswap x), C) instructions when C is 16 or 32 (PR #105375)

[via llvm-commits]

DTeachs wrote:

> GCC compiles the built-in function `__builtin_bswap16`, to the ARM instruction rev16, which reverses the byte order of 16-bit data. On the other Clang compiles the same built-in function to e.g.
> 
> ```
>         rev     w8, w0
>         lsr     w0, w8, #16
> ```
> 
> i.e. it performs a byte reversal of a 32-bit register, (which moves the lower half, which contains the 16-bit data, to the upper half) and then right shifts the reversed 16-bit data back to the lower half of the register. We can improve Clang codegen by generating `rev16` instead of `rev` and `lsr`, like GCC.

The problem is that this patch is incorrect because in the tests, the IR requests an i32, in which case, the top bits are needed, so rev16 would be incorrect. 

https://github.com/llvm/llvm-project/pull/105375