[llvm] [AArch64] [CodeGen] [REV] Generate revC for all (srl (bswap x), C) instructions when C is 16 or 32 (PR #105375)
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Tue Aug 20 14:02:41 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: None (adprasad-nvidia)
<details>
<summary>Changes</summary>
GCC compiles the built-in function `__builtin_bswap16`, to the ARM instruction rev16, which reverses the byte order of 16-bit data. On the other Clang compiles the same built-in function to e.g.
```
rev w8, w0
lsr w0, w8, #<!-- -->16
```
i.e. it performs a byte reversal of a 32-bit register, (which moves the lower half, which contains the 16-bit data, to the upper half) and then right shifts the reversed 16-bit data back to the lower half of the register.
We can improve Clang codegen by generating `rev16` instead of `rev` and `lsr`, like GCC.
---
Full diff: https://github.com/llvm/llvm-project/pull/105375.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+3-3)
- (modified) llvm/test/CodeGen/AArch64/arm64-rev.ll (+13-28)
- (modified) llvm/test/CodeGen/AArch64/bswap.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/memcmp.ll (+5-10)
- (modified) llvm/test/CodeGen/AArch64/merge-trunc-store.ll (+4-8)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index a9324af5beb784..227ed141075582 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2825,9 +2825,9 @@ def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
-// Match (srl (bswap x), C) -> revC if the upper bswap bits are known zero.
-def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;
-def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;
+// Match (srl (bswap x), C) -> revC.
+def : Pat<(srl (bswap GPR32:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;
+def : Pat<(srl (bswap GPR64:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;
def : Pat<(or (and (srl GPR64:$Rn, (i64 8)), (i64 0x00ff00ff00ff00ff)),
(and (shl GPR64:$Rn, (i64 8)), (i64 0xff00ff00ff00ff00))),
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index f548a0e01feee6..5973a6a0cf113f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -27,15 +27,13 @@ entry:
define i32 @test_rev_w_srl16(i16 %a) {
; CHECK-SD-LABEL: test_rev_w_srl16:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: rev w8, w0
-; CHECK-SD-NEXT: lsr w0, w8, #16
+; CHECK-SD-NEXT: rev16 w0, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_rev_w_srl16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w0, #0xffff
-; CHECK-GI-NEXT: rev w8, w8
-; CHECK-GI-NEXT: lsr w0, w8, #16
+; CHECK-GI-NEXT: rev16 w0, w8
; CHECK-GI-NEXT: ret
entry:
%0 = zext i16 %a to i32
@@ -48,8 +46,7 @@ define i32 @test_rev_w_srl16_load(ptr %a) {
; CHECK-LABEL: test_rev_w_srl16_load:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: rev w8, w8
-; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: rev16 w0, w8
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr %a
@@ -71,8 +68,7 @@ define i32 @test_rev_w_srl16_add(i8 %a, i8 %b) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w1, #0xff
; CHECK-GI-NEXT: add w8, w8, w0, uxtb
-; CHECK-GI-NEXT: rev w8, w8
-; CHECK-GI-NEXT: lsr w0, w8, #16
+; CHECK-GI-NEXT: rev16 w0, w8
; CHECK-GI-NEXT: ret
entry:
%0 = zext i8 %a to i32
@@ -89,15 +85,13 @@ define i64 @test_rev_x_srl32(i32 %a) {
; CHECK-SD-LABEL: test_rev_x_srl32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SD-NEXT: rev x8, x0
-; CHECK-SD-NEXT: lsr x0, x8, #32
+; CHECK-SD-NEXT: rev32 x0, x0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_rev_x_srl32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov w8, w0
-; CHECK-GI-NEXT: rev x8, x8
-; CHECK-GI-NEXT: lsr x0, x8, #32
+; CHECK-GI-NEXT: rev32 x0, x8
; CHECK-GI-NEXT: ret
entry:
%0 = zext i32 %a to i64
@@ -110,8 +104,7 @@ define i64 @test_rev_x_srl32_load(ptr %a) {
; CHECK-LABEL: test_rev_x_srl32_load:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: rev x8, x8
-; CHECK-NEXT: lsr x0, x8, #32
+; CHECK-NEXT: rev32 x0, x8
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr %a
@@ -122,18 +115,11 @@ entry:
}
define i64 @test_rev_x_srl32_shift(i64 %a) {
-; CHECK-SD-LABEL: test_rev_x_srl32_shift:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ubfx x8, x0, #2, #29
-; CHECK-SD-NEXT: rev32 x0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_rev_x_srl32_shift:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: ubfx x8, x0, #2, #29
-; CHECK-GI-NEXT: rev x8, x8
-; CHECK-GI-NEXT: lsr x0, x8, #32
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_rev_x_srl32_shift:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ubfx x8, x0, #2, #29
+; CHECK-NEXT: rev32 x0, x8
+; CHECK-NEXT: ret
entry:
%0 = shl i64 %a, 33
%1 = lshr i64 %0, 35
@@ -472,8 +458,7 @@ define void @test_rev16_truncstore() {
; CHECK-GI-NEXT: .LBB30_1: // %cleanup
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: ldrh w8, [x8]
-; CHECK-GI-NEXT: rev w8, w8
-; CHECK-GI-NEXT: lsr w8, w8, #16
+; CHECK-GI-NEXT: rev16 w8, w8
; CHECK-GI-NEXT: strh w8, [x8]
; CHECK-GI-NEXT: tbz wzr, #0, .LBB30_1
; CHECK-GI-NEXT: .LBB30_2: // %fail
diff --git a/llvm/test/CodeGen/AArch64/bswap.ll b/llvm/test/CodeGen/AArch64/bswap.ll
index 071613b9cc011e..2a60abdc2308f0 100644
--- a/llvm/test/CodeGen/AArch64/bswap.ll
+++ b/llvm/test/CodeGen/AArch64/bswap.ll
@@ -6,8 +6,7 @@
define i16 @bswap_i16(i16 %a){
; CHECK-LABEL: bswap_i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: rev w8, w0
-; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: rev16 w0, w0
; CHECK-NEXT: ret
%3 = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %3
diff --git a/llvm/test/CodeGen/AArch64/memcmp.ll b/llvm/test/CodeGen/AArch64/memcmp.ll
index 4da7c8c95a4e4f..0a6a03844128c3 100644
--- a/llvm/test/CodeGen/AArch64/memcmp.ll
+++ b/llvm/test/CodeGen/AArch64/memcmp.ll
@@ -39,9 +39,8 @@ define i32 @length2(ptr %X, ptr %Y) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: ldrh w9, [x1]
-; CHECK-NEXT: rev w8, w8
+; CHECK-NEXT: rev16 w8, w8
; CHECK-NEXT: rev w9, w9
-; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: sub w0, w8, w9, lsr #16
; CHECK-NEXT: ret
%m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 2) nounwind
@@ -93,9 +92,8 @@ define i1 @length2_lt(ptr %X, ptr %Y) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: ldrh w9, [x1]
-; CHECK-NEXT: rev w8, w8
+; CHECK-NEXT: rev16 w8, w8
; CHECK-NEXT: rev w9, w9
-; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: sub w8, w8, w9, lsr #16
; CHECK-NEXT: lsr w0, w8, #31
; CHECK-NEXT: ret
@@ -109,9 +107,8 @@ define i1 @length2_gt(ptr %X, ptr %Y) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: ldrh w9, [x1]
-; CHECK-NEXT: rev w8, w8
+; CHECK-NEXT: rev16 w8, w8
; CHECK-NEXT: rev w9, w9
-; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: sub w8, w8, w9, lsr #16
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cset w0, gt
@@ -536,10 +533,8 @@ define i32 @length10(ptr %X, ptr %Y) nounwind {
; CHECK-NEXT: // %bb.1: // %loadbb1
; CHECK-NEXT: ldrh w8, [x0, #8]
; CHECK-NEXT: ldrh w9, [x1, #8]
-; CHECK-NEXT: rev w8, w8
-; CHECK-NEXT: rev w9, w9
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: lsr w9, w9, #16
+; CHECK-NEXT: rev16 w8, w8
+; CHECK-NEXT: rev16 w9, w9
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: b.ne .LBB32_3
; CHECK-NEXT: // %bb.2:
diff --git a/llvm/test/CodeGen/AArch64/merge-trunc-store.ll b/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
index b161d746ad11d5..4fcd030db1bace 100644
--- a/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
@@ -10,8 +10,7 @@ define void @le_i16_to_i8(i16 %x, ptr %p0) {
;
; BE-LABEL: le_i16_to_i8:
; BE: // %bb.0:
-; BE-NEXT: rev w8, w0
-; BE-NEXT: lsr w8, w8, #16
+; BE-NEXT: rev16 w8, w0
; BE-NEXT: strh w8, [x1]
; BE-NEXT: ret
%sh1 = lshr i16 %x, 8
@@ -31,8 +30,7 @@ define void @le_i16_to_i8_order(i16 %x, ptr %p0) {
;
; BE-LABEL: le_i16_to_i8_order:
; BE: // %bb.0:
-; BE-NEXT: rev w8, w0
-; BE-NEXT: lsr w8, w8, #16
+; BE-NEXT: rev16 w8, w0
; BE-NEXT: strh w8, [x1]
; BE-NEXT: ret
%sh1 = lshr i16 %x, 8
@@ -47,8 +45,7 @@ define void @le_i16_to_i8_order(i16 %x, ptr %p0) {
define void @be_i16_to_i8_offset(i16 %x, ptr %p0) {
; LE-LABEL: be_i16_to_i8_offset:
; LE: // %bb.0:
-; LE-NEXT: rev w8, w0
-; LE-NEXT: lsr w8, w8, #16
+; LE-NEXT: rev16 w8, w0
; LE-NEXT: sturh w8, [x1, #11]
; LE-NEXT: ret
;
@@ -69,8 +66,7 @@ define void @be_i16_to_i8_offset(i16 %x, ptr %p0) {
define void @be_i16_to_i8_order(i16 %x, ptr %p0) {
; LE-LABEL: be_i16_to_i8_order:
; LE: // %bb.0:
-; LE-NEXT: rev w8, w0
-; LE-NEXT: lsr w8, w8, #16
+; LE-NEXT: rev16 w8, w0
; LE-NEXT: strh w8, [x1]
; LE-NEXT: ret
;
``````````
</details>
https://github.com/llvm/llvm-project/pull/105375
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