[llvm] [AArch64] optimise SVE cmp intrinsics with no active lanes (PR #104779)

[via llvm-commits]

================
@@ -2131,6 +2135,25 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
   case Intrinsic::aarch64_sve_st4:
   case Intrinsic::aarch64_sve_st4q:
     return instCombineSVENoActiveUnaryErase(IC, II, 4);
+  case Intrinsic::aarch64_sve_cmpeq:
----------------
Lukacma wrote:

This is a good point. [AAPCS](https://github.com/ARM-software/abi-aa/blob/2982a9f3b512a5bfdc9e3fea5d3b298f9165c36b/aapcs64/aapcs64.rst) says this:

> The N, Z, C and V flags are undefined on entry to and return from a public interface.

I think intrinsic call is a public interface, but I am not sure. @paulwalker-arm could you help clarify this? 

https://github.com/llvm/llvm-project/pull/104779