[llvm] [AArch64] optimise SVE cmp intrinsics with no active lanes (PR #104779)

[Paul Walker via llvm-commits]

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@@ -2131,6 +2135,25 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
   case Intrinsic::aarch64_sve_st4:
   case Intrinsic::aarch64_sve_st4q:
     return instCombineSVENoActiveUnaryErase(IC, II, 4);
+  case Intrinsic::aarch64_sve_cmpeq:
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paulwalker-arm wrote:

The compare intrinsics (and C builtins) have no side effects and so the fact some of them may code generate to instructions that set the condition codes is not relevant.

>From the ACLE's point of view the result of a compare builtin should be tested via the `svptest` builtins.  The compiler will see this sequence and decide whether it can use the fact a compare instruction also sets the condition codes to its advantage.

https://github.com/llvm/llvm-project/pull/104779