[llvm] [AArch64] optimise SVE cmp intrinsics with no active lanes (PR #104779)

[via llvm-commits]

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@@ -2131,6 +2135,25 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
   case Intrinsic::aarch64_sve_st4:
   case Intrinsic::aarch64_sve_st4q:
     return instCombineSVENoActiveUnaryErase(IC, II, 4);
+  case Intrinsic::aarch64_sve_cmpeq:
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SpencerAbson wrote:

As these integer comparison intrinsics compile to instructions that set the status register (even if the predicate is all inactive, see use of [PredTest](https://developer.arm.com/documentation/ddi0602/2024-06/Shared-Pseudocode/aarch64-functions-sve?lang=en#impl-aarch64.PredTest.3) in [CMP<cc>)](https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions/CMP-cc---wide-elements---Compare-vector-to-64-bit-wide-elements-), it might be worth referencing where the [ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#programmers-model-of-global-state) declares this part of the global state as undefined? 

https://github.com/llvm/llvm-project/pull/104779