[llvm] [RISCV] Use zext.[b/w/h] instead of th.extu for bitfield extraction (PR #101605)

[via llvm-commits]

joshua-arch1 wrote:

> > > > Is there a xuantie core that supports both zbb and xtheadbb?
> > > 
> > > 
> > > Yeah, I have done some experiments on XuanTie C908 processors, extu rd,rs,15,0 performs worse than zext.h rd,rs and extu rd,rs,31,0 performs worse than zext.w rd,rs.
> > 
> > 
> > I would have expected that both forms decode to the same u-ops Looks like those are different implementations in the core.
> > That said, I would recommend we use a new `Feature...` definition and test to see which code-generation strategy a given code prefers.
> 
> How would the new `Feature...` get set? If its not connected to a specific -mcpu/-mtune then user would have to write something like `-Xclang -target-feature -Xclang +new-feature`.

Yeah, I have the same question. Also, even if we use the feature, we need to have a default code generation. From my perspective, I prefer to use the standard instruction by default.

https://github.com/llvm/llvm-project/pull/101605