[llvm] [GlobalIsel][AArch64] Replace N bit G_ADD with N/2 bit G_ADD if the lower bits are known to be zeros (PR #101327)

[Thorsten Schütt via llvm-commits]

tschuett wrote:

> > > This sounds like an interesting optimization. Why doesn't it happen already after legalizing the add?
> > 
> > 
> > Where/why would you expect this to already happen?
> 
> The legalizer will split the ADD into G_UADDO and G_UADDE. A post legalizer combiner should then be able to see that the G_UADDO created for the lower half has an all 0 input. That's how it's handed in SelectionDAG. Maybe such a post legalizer combine is missing for G_UADDO?

We rely on https://github.com/llvm/llvm-project/blob/5dfdac74cadd9483a66eb17e51dc632b554cccb1/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp#L7215

https://github.com/llvm/llvm-project/pull/101327