[llvm] [GlobalIsel][AArch64] Replace N bit G_ADD with N/2 bit G_ADD if the lower bits are known to be zeros (PR #101327)

[Craig Topper via llvm-commits]

topperc wrote:

> > This sounds like an interesting optimization. Why doesn't it happen already after legalizing the add?
> 
> Where/why would you expect this to already happen?

The legalizer will split the ADD into G_UADDO and G_UADDE. A post legalizer combiner should then be able to see that the G_UADDO created for the lower half has an all 0 input. Maybe such a post legalizer combine is missing for G_UADDO?

https://github.com/llvm/llvm-project/pull/101327