[llvm] [GlobalIsel][AArch64] Replace N bit G_ADD with N/2 bit G_ADD if the lower bits are known to be zeros (PR #101327)

[Matt Arsenault via llvm-commits]

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@@ -5099,6 +5099,67 @@ bool CombinerHelper::matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo) {
   return true;
 }
 
+bool CombinerHelper::matchAddWithKnownZeroLowerHalfBits(MachineInstr &MI,
+                                                        BuildFnTy &MatchInfo) {
+  GAdd *Add = cast<GAdd>(&MI);
+
+  const Register DstReg = Add->getReg(0);
+  const LLT FullTy = MRI.getType(DstReg);
+
+  if (!FullTy.isScalar())
+    return false;
+
+  const std::uint64_t FullSize = FullTy.getSizeInBits();
+  const std::uint64_t HalfSize = (FullSize + 1) / 2;
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arsenm wrote:

Don't need these std::s

https://github.com/llvm/llvm-project/pull/101327