[llvm] [GlobalIsel][AArch64] Replace N bit G_ADD with N/2 bit G_ADD if the lower bits are known to be zeros (PR #101327)

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KRM7 wrote:

> This sounds like an interesting optimization. Why doesn't it happen already after legalizing the add?

Where/why would you expect this to already happen?

https://github.com/llvm/llvm-project/pull/101327