[llvm] [AArch64] Add tests for redundant csel instructions. NFC (PR #101014)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 30 09:25:32 PDT 2024
https://github.com/citymarina updated https://github.com/llvm/llvm-project/pull/101014
>From 7ca61923e5d60da3ce39045d2973577cdc24a522 Mon Sep 17 00:00:00 2001
From: Marina Taylor <marina_taylor at apple.com>
Date: Mon, 29 Jul 2024 14:58:58 +0100
Subject: [PATCH 1/2] [AArch64] Add tests for redundant csel instructions. NFC
---
llvm/test/CodeGen/AArch64/peephole-csel.ll | 29 +++++
llvm/test/CodeGen/AArch64/peephole-csel.mir | 112 ++++++++++++++++++++
2 files changed, 141 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/peephole-csel.ll
create mode 100644 llvm/test/CodeGen/AArch64/peephole-csel.mir
diff --git a/llvm/test/CodeGen/AArch64/peephole-csel.ll b/llvm/test/CodeGen/AArch64/peephole-csel.ll
new file mode 100644
index 0000000000000..9a1ec393eacc2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define void @peephole_csel(ptr %dst, i1 %0, i1 %cmp) {
+; CHECK-LABEL: peephole_csel:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: tst w2, #0x1
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: csel x9, xzr, xzr, eq
+; CHECK-NEXT: tst w1, #0x1
+; CHECK-NEXT: csel x8, x8, x9, eq
+; CHECK-NEXT: str x8, [x0]
+; CHECK-NEXT: ret
+entry:
+ br i1 %0, label %then, label %exit
+
+then: ; preds = %entry
+ %cmp1 = icmp eq i32 0, 0
+ br i1 %cmp, label %true, label %exit
+
+true: ; preds = %then
+ %and.i = lshr i64 0, 0
+ br label %exit
+
+exit: ; preds = %true, %then, %entry
+ %x = phi i64 [ 0, %true ], [ 0, %then ], [ 1, %entry ]
+ store i64 %x, ptr %dst, align 8
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/peephole-csel.mir b/llvm/test/CodeGen/AArch64/peephole-csel.mir
new file mode 100644
index 0000000000000..5077441a33788
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.mir
@@ -0,0 +1,112 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s
+
+---
+name: peephole_cselxr_same
+registers:
+ - { id: 1, class: gpr64, preferred-register: '' }
+ - { id: 2, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '$x0', virtual-reg: '%1' }
+ - { reg: '$x1', virtual-reg: '%2' }
+body: |
+ bb.0.entry:
+ liveins: $x0, $x1
+
+ ; CHECK-LABEL: name: peephole_cselxr_same
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY1]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ %3:gpr64 = COPY $x1
+ %4:gpr64 = COPY $x0
+ $xzr = ANDSXri %3, 0, implicit-def $nzcv
+ %5:gpr64 = CSELXr %4, %4, 0, implicit $nzcv
+ RET_ReallyLR
+
+...
+---
+name: peephole_cselwr_same
+registers:
+ - { id: 1, class: gpr32, preferred-register: '' }
+ - { id: 2, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '$w0', virtual-reg: '%1' }
+ - { reg: '$w1', virtual-reg: '%2' }
+body: |
+ bb.0.entry:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: peephole_cselwr_same
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ %3:gpr32 = COPY $w1
+ %4:gpr32 = COPY $w0
+ $wzr = ANDSWri %3, 0, implicit-def $nzcv
+ %5:gpr32 = CSELWr %4, %4, 0, implicit $nzcv
+ RET_ReallyLR
+
+...
+---
+name: peephole_cselxr_different
+registers:
+ - { id: 1, class: gpr64, preferred-register: '' }
+ - { id: 2, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '$x0', virtual-reg: '%1' }
+ - { reg: '$x1', virtual-reg: '%2' }
+body: |
+ bb.0.entry:
+ liveins: $x0, $x1
+
+ ; CHECK-LABEL: name: peephole_cselxr_different
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ %3:gpr64 = COPY $x1
+ %4:gpr64 = COPY $x0
+ $xzr = ANDSXri %3, 0, implicit-def $nzcv
+ %5:gpr64 = CSELXr %3, %4, 0, implicit $nzcv
+ RET_ReallyLR
+
+...
+---
+name: peephole_cselwr_different
+registers:
+ - { id: 1, class: gpr32, preferred-register: '' }
+ - { id: 2, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '$w0', virtual-reg: '%1' }
+ - { reg: '$w1', virtual-reg: '%2' }
+body: |
+ bb.0.entry:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: peephole_cselwr_different
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ %3:gpr32 = COPY $w1
+ %4:gpr32 = COPY $w0
+ $wzr = ANDSWri %3, 0, implicit-def $nzcv
+ %5:gpr32 = CSELWr %3, %4, 0, implicit $nzcv
+ RET_ReallyLR
+
+...
+
>From bf7f7fb183186abcdebea5de0421749096b395ef Mon Sep 17 00:00:00 2001
From: Marina Taylor <marina_taylor at apple.com>
Date: Tue, 30 Jul 2024 17:24:53 +0100
Subject: [PATCH 2/2] Replace dead instructions with llvm.donothing()
---
llvm/test/CodeGen/AArch64/peephole-csel.ll | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/peephole-csel.ll b/llvm/test/CodeGen/AArch64/peephole-csel.ll
index 9a1ec393eacc2..3f92943b11eb1 100644
--- a/llvm/test/CodeGen/AArch64/peephole-csel.ll
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.ll
@@ -15,11 +15,14 @@ entry:
br i1 %0, label %then, label %exit
then: ; preds = %entry
- %cmp1 = icmp eq i32 0, 0
+ ; The donothing() is needed to make make this block less interesting to
+ ; SimplifyCFG. Otherwise we may not get the csel that we want to test.
+ call void @llvm.donothing()
br i1 %cmp, label %true, label %exit
true: ; preds = %then
- %and.i = lshr i64 0, 0
+ ; Same as above
+ call void @llvm.donothing()
br label %exit
exit: ; preds = %true, %then, %entry
More information about the llvm-commits
mailing list