[llvm] [MachinePipeliner] Fix instruction order with physical register (PR #99264)

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Mon Jul 29 09:54:41 PDT 2024

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https://github.com/dpenry approved this pull request.

These changes make sense to me. I would like to see comments from other reviewers.

https://github.com/llvm/llvm-project/pull/99264

Previous message: [llvm] [InstCombine] Add an option to skip simplification on call instruction where a non-void return value is expected while the callee returns void (PR #98536)
Next message: [llvm] [MachinePipeliner] Fix instruction order with physical register (PR #99264)
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