[llvm] [SelectionDAG] Simplify vselect true, T, F -> T (PR #100992)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 04:05:25 PDT 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/100992
>From 52d1103acba7ada6632f45b0fd774ff5de19e939 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 17:02:13 +0800
Subject: [PATCH 1/4] Precommit tests
---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vp-select.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
new file mode 100644
index 0000000000000..a218230e126d7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+
+define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
+; CHECK-LABEL: all_ones:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 32
+; CHECK-NEXT: srli a0, a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
+ ret <vscale x 1 x i64> %v
+}
>From 4efe9db41bce77dc626e2a432020b08b14c6d494 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 17:11:25 +0800
Subject: [PATCH 2/4] [SelectionDAG] Simplify vselect true, T, F -> T
This addresses a TODO where we can fold a vselect to it's true operand if the boolean is known to be all trues, checking getBooleanContents.
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 20 ++++++++++++++++---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 5 -----
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index daebcdabda984..1876bf3f18c21 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9927,13 +9927,27 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
return CondC->isZero() ? F : T;
- // TODO: This should simplify VSELECT with non-zero constant condition using
- // something like this (but check boolean contents to be complete?):
if (ConstantSDNode *CondC = isConstOrConstSplat(Cond, /*AllowUndefs*/ false,
- /*AllowTruncation*/ true))
+ /*AllowTruncation*/ true)) {
if (CondC->isZero())
return F;
+ switch (TLI->getBooleanContents(Cond.getValueType())) {
+ case TargetLowering::UndefinedBooleanContent:
+ if (CondC->getAPIntValue()[0])
+ return T;
+ break;
+ case TargetLowering::ZeroOrOneBooleanContent:
+ if (CondC->isOne())
+ return T;
+ break;
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
+ if (CondC->isAllOnes())
+ return T;
+ break;
+ }
+ }
+
// select ?, T, T --> T
if (T == F)
return T;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
index a218230e126d7..5c903791927c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -4,11 +4,6 @@
define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
; CHECK-LABEL: all_ones:
; CHECK: # %bb.0:
-; CHECK-NEXT: slli a0, a0, 32
-; CHECK-NEXT: srli a0, a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
ret <vscale x 1 x i64> %v
>From 7417903a6c15bab9f3064db0738483aa1bb04a77 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 18:05:38 +0800
Subject: [PATCH 3/4] Extract out isBoolConstant
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 5 +++
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 ++--------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 42 +++++++++----------
3 files changed, 27 insertions(+), 41 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 6a80c8c7216f6..5035e298081fe 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2320,6 +2320,11 @@ class SelectionDAG {
isConstantFPBuildVectorOrConstantFP(N);
}
+ /// Check if a value \op N is a true or false constant using the target's
+ /// BooleanContent for its type.
+ std::optional<bool> isBoolConstant(SDValue N,
+ bool AllowTruncation = false) const;
+
/// Set CallSiteInfo to be associated with Node.
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo) {
SDEI[Node].CSInfo = std::move(CallInfo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 060e66175d965..27bdab3d83833 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3260,26 +3260,11 @@ static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
if (V.getOpcode() != ISD::XOR)
return SDValue();
- ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
- if (!Const)
+ auto IsFlip = DAG.isBoolConstant(V.getOperand(1));
+ if (!IsFlip)
return SDValue();
- EVT VT = V.getValueType();
-
- bool IsFlip = false;
- switch(TLI.getBooleanContents(VT)) {
- case TargetLowering::ZeroOrOneBooleanContent:
- IsFlip = Const->isOne();
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- IsFlip = Const->isAllOnes();
- break;
- case TargetLowering::UndefinedBooleanContent:
- IsFlip = (Const->getAPIntValue() & 0x01) == 1;
- break;
- }
-
- if (IsFlip)
+ if (*IsFlip)
return V.getOperand(0);
if (Force)
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1876bf3f18c21..cc55cefcb376a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9924,29 +9924,8 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
// select true, T, F --> T
// select false, T, F --> F
- if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
- return CondC->isZero() ? F : T;
-
- if (ConstantSDNode *CondC = isConstOrConstSplat(Cond, /*AllowUndefs*/ false,
- /*AllowTruncation*/ true)) {
- if (CondC->isZero())
- return F;
-
- switch (TLI->getBooleanContents(Cond.getValueType())) {
- case TargetLowering::UndefinedBooleanContent:
- if (CondC->getAPIntValue()[0])
- return T;
- break;
- case TargetLowering::ZeroOrOneBooleanContent:
- if (CondC->isOne())
- return T;
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- if (CondC->isAllOnes())
- return T;
- break;
- }
- }
+ if (auto CondC = isBoolConstant(Cond, /*AllowTruncation*/ true))
+ return *CondC ? T : F;
// select ?, T, T --> T
if (T == F)
@@ -13138,6 +13117,23 @@ SDNode *SelectionDAG::isConstantFPBuildVectorOrConstantFP(SDValue N) const {
return nullptr;
}
+std::optional<bool> SelectionDAG::isBoolConstant(SDValue N,
+ bool AllowTruncation) const {
+ ConstantSDNode *Const = isConstOrConstSplat(N, false, AllowTruncation);
+ if (!Const)
+ return std::nullopt;
+
+ switch (TLI->getBooleanContents(N.getValueType())) {
+ case TargetLowering::ZeroOrOneBooleanContent:
+ return Const->isOne();
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
+ return Const->isAllOnes();
+ break;
+ case TargetLowering::UndefinedBooleanContent:
+ return Const->getAPIntValue()[0];
+ }
+}
+
void SelectionDAG::createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
assert(!Node->OperandList && "Node already has operands");
assert(SDNode::getMaxNumOperands() >= Vals.size() &&
>From 15400c147cd181ece55f9db6141e6cad79781e66 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 19:05:04 +0800
Subject: [PATCH 4/4] Add all false test
---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
index 5c903791927c6..c8a048971a803 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -8,3 +8,12 @@ define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64>
%v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
ret <vscale x 1 x i64> %v
}
+
+define <vscale x 1 x i64> @all_zeroes(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
+; CHECK-LABEL: all_zeroes:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 false), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
+ ret <vscale x 1 x i64> %v
+}
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