[llvm] [SelectionDAG] Simplify vselect true, T, F -> T (PR #100992)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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lukel97 wrote:

This is already the de-facto for the RVV in-tree tests:
```
$ git grep "\-verify\-machineinstrs" -- llvm/test/CodeGen/RISCV/rvv | wc -l
    2017
```

I get your point about slow test times but we rely very heavily on this for coverage on RISCVInsertVSETVLI. Should we create a separate issue to discuss this outside of this PR

https://github.com/llvm/llvm-project/pull/100992