[llvm] [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (PR #100966)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

> > Another special case with slli+slli (sampled from pybind11): https://godbolt.org/z/rc95a37ej
> 
> Is that something we should handle in generic DAGCombine? The X86 code is also bad. https://godbolt.org/z/7Tv3Gsc5f

```
Optimized legalized selection DAG: %bb.0 'func0000000000000005:entry'
SelectionDAG has 16 nodes:
  t0: ch,glue = EntryToken
              t4: i64,ch = CopyFromReg t0, Register:i64 %1
            t6: i64 = AssertSext t4, ValueType:ch:i16
          t19: i64 = shl t6, Constant:i64<9>
        t20: i64 = sign_extend_inreg t19, ValueType:ch:i16
      t21: i64 = sra t20, Constant:i64<15>
      t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t15: i64 = add nsw t21, t2
  t17: ch,glue = CopyToReg t0, Register:i64 $x10, t15
  t18: ch = RISCVISD::RET_GLUE t17, Register:i64 $x10, t17:1


===== Instruction selection begins: %bb.0 'entry'
```

Unfortunately we cannot handle this in DAGCombine since it happens in ISel.
Do you mean to expand `sign_extend_inreg X, i16` into `(X << 48) s>> 48` in DAGCombine?


https://github.com/llvm/llvm-project/pull/100966