[llvm] [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (PR #100966)

[Craig Topper via llvm-commits]

topperc wrote:

> Another special case with slli+slli (sampled from pybind11): https://godbolt.org/z/rc95a37ej

Is that something we should handle in generic DAGCombine? The X86 code is also bad.

https://github.com/llvm/llvm-project/pull/100966