[llvm] [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (PR #100966)

[Craig Topper via llvm-commits]

topperc wrote:

> t20: i64 = sign_extend_inreg t19, ValueType:ch:i16
>       t21: i64 = sra t20, Constant:i64<15>

I wouldn't want to expand sign_extend_inreg by itself.

But maybe we should expand this into a sra+shl during DAGCombine.

```
        t20: i64 = sign_extend_inreg t19, ValueType:ch:i16
      t21: i64 = sra t20, Constant:i64<15>
```

https://github.com/llvm/llvm-project/pull/100966