[llvm] [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (PR #100966)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

I don't think it is a good way to fix these kinds of issues. I prefer to do a final clean up for slli+slli/srli+srli pairs in `RISCVDAGToDAGISel::PostprocessISelDAG`.

Another special case with slli+slli (sampled from pybind11): https://godbolt.org/z/rc95a37ej
```
; bin/llc -mtriple=riscv64 -mattr=+zbb test.ll -o -
define i64 @func0000000000000005(i64 %0, i16 signext %1) #0 {
entry:
  %2 = shl i16 %1, 9
  %sext = ashr i16 %2, 15
  %3 = sext i16 %sext to i64
  %4 = add nsw i64 %3, %0
  ret i64 %4
}
```
```
func0000000000000005:                   # @func0000000000000005
        slli    a1, a1, 9
        slli    a1, a1, 48
        srai    a1, a1, 63
        add     a0, a1, a0
        ret
```


https://github.com/llvm/llvm-project/pull/100966