[llvm] [RISCV] Add unit strided load/store to whole register peephole (PR #100116)

[Luke Lau via llvm-commits]

lukel97 wrote:

Good eye, I went ahead and tried removing that code but it looks like we get some slight regressions due to some missed DAG combines because it's now lowered to a RISC-V intrinsic instead of a generic ISD::LOAD. 

I think we should still be able to do these combines on the pre-op-legalized form though, will take a look. 

https://github.com/llvm/llvm-project/pull/100116