[llvm] [RISCV] Add unit strided load/store to whole register peephole (PR #100116)

[Philip Reames via llvm-commits]

preames wrote:

JFYI, this may have made a bit of code in both lowerFixedLengthVectorLoadToRVV and lowerFixedLengthVectorStoreToRVV dead.  Would be worth checking and see if the whole register cases can be removed now.

https://github.com/llvm/llvm-project/pull/100116