[llvm] [RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (PR #98111)

[Luke Lau via llvm-commits]

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@@ -116,7 +116,7 @@ define void @stride_one_store(i64 %n, ptr %p) {
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 0
-; RV64-NEXT:    vs1r.v v8, (a1)
+; RV64-NEXT:    vse64.v v8, (a1)
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lukel97 wrote:

Rather than do a vp_load -> vp combine, I've instead replaced the whole register load patterns with a more generic peephole in #100116. I think that should fix this case.

https://github.com/llvm/llvm-project/pull/98111