[llvm] [RISCV] vsetvl pseudo may cross inline asm without sideeffect (PR #97794)

[Kito Cheng via llvm-commits]

kito-cheng wrote:

Hmm, I am also thinking that we may add few more word on the intrinsic document side, to encourage.suggest user add those CSR as dependency or clobber.

```
# Mixing inline assembly and intrinsics
The compiler will be conservative to registers (vtype, vxrm, frm) when encountering inline assembly. Users should be aware that mixing uses of intrinsics and inline assembly will result in extra save and restore.
```

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#mixing-inline-assembly-and-intrinsics

https://github.com/llvm/llvm-project/pull/97794