[llvm] [AArch64] All bits of an exact right shift are demanded (PR #97448)
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 8 09:32:59 PDT 2024
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@@ -22142,6 +22142,10 @@ static SDValue performVectorShiftCombine(SDNode *N,
if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm)
return Op.getOperand(0);
+ // If the right shift is exact, the shifted out bits matter.
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momchil-velikov wrote:
I wrote that in the commit message
> However, these elements need to stay zero if the right shift is exact, or otherwise we will be introducing undefined behavior.
https://github.com/llvm/llvm-project/pull/97448
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