[llvm] [AArch64] All bits of an exact right shift are demanded (PR #97448)

[Shu-Chun Weng via llvm-commits]

================
@@ -22142,6 +22142,10 @@ static SDValue performVectorShiftCombine(SDNode *N,
     if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm)
       return Op.getOperand(0);
 
+  // If the right shift is exact, the shifted out bits matter.
----------------
scweng wrote:

(Somehow didn't send this out before -- posting for posterity.)

https://github.com/llvm/llvm-project/pull/97448